add register specs to pipeline in/out so that they can be used to connect up

[soc.git] / src / soc / fu / shift_rot / pipe_data.py

diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py
index 0c0e6cab54db84a05bce85ae1b8bc1276540c3b8..eed4dffe4d37787863c57213154df910a33914f6 100644 (file)
--- a/src/soc/fu/shift_rot/pipe_data.py
+++ b/src/soc/fu/shift_rot/pipe_data.py
@@ -6,6 +6,11 @@ from soc.fu.alu.pipe_data import IntegerData
 
 
 class ShiftRotInputData(IntegerData):
+    regspec = [('INT', 'ra', '0:63'),
+               ('INT', 'rs', '0:63'),
+               ('INT', 'rb', '0:63'),
+               ('XER', 'xer_so', '32'),
+               ('XER', 'xer_ca', '34,45')]
     def __init__(self, pspec):
         super().__init__(pspec)
         self.ra = Signal(64, reset_less=True) # RA