class TestCase:
def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
- msr=0):
+ msr=0,
+ do_sim=True,
+ extra_break_addr=None):
self.program = program
self.name = name
self.cr = cr
self.mem = mem
self.msr = msr
+ self.do_sim = do_sim
+ self.extra_break_addr = extra_break_addr
+
class ALUHelpers:
def get_sim_msr(res, sim, dec2):
res['msr'] = sim.msr.value
+ def get_sim_slow_spr1(res, sim, dec2):
+ spr1_en = yield dec2.e.read_spr1.ok
+ if spr1_en:
+ spr1_sel = yield dec2.e.read_spr1.data
+ spr1_data = sim.spr[spr1_sel].value
+ res['spr1'] = spr1_data
+
def get_sim_fast_spr1(res, sim, dec2):
fast1_en = yield dec2.e.read_fast1.ok
if fast1_en:
res['rc'] = sim.gpr(data).value
def get_rd_sim_xer_ca(res, sim, dec2):
- cry_in = yield dec2.e.input_carry
- if cry_in == CryIn.CA.value:
+ cry_in = yield dec2.e.do.input_carry
+ xer_in = yield dec2.e.xer_in
+ if xer_in or cry_in == CryIn.CA.value:
expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
res['xer_ca'] = expected_carry | (expected_carry32 << 1)
if 'rb' in inp:
yield alu.p.data_i.rb.eq(inp['rb'])
# If there's an immediate, set the B operand to that
- imm_ok = yield dec2.e.imm_data.imm_ok
+ imm_ok = yield dec2.e.do.imm_data.imm_ok
if imm_ok:
- data2 = yield dec2.e.imm_data.imm
+ data2 = yield dec2.e.do.imm_data.imm
yield alu.p.data_i.rb.eq(data2)
def set_int_rc(alu, dec2, inp):
yield alu.p.data_i.xer_so.eq(so)
def set_msr(alu, dec2, inp):
+ print ("TODO: deprecate set_msr")
if 'msr' in inp:
yield alu.p.data_i.msr.eq(inp['msr'])
def set_cia(alu, dec2, inp):
+ print ("TODO: deprecate set_cia")
if 'cia' in inp:
yield alu.p.data_i.cia.eq(inp['cia'])
res['cr_a'] = yield alu.n.data_o.cr0.data
def get_xer_so(res, alu, dec2):
- oe = yield dec2.e.oe.oe
- oe_ok = yield dec2.e.oe.ok
- if oe and oe_ok:
+ oe = yield dec2.e.do.oe.oe
+ oe_ok = yield dec2.e.do.oe.ok
+ xer_out = yield dec2.e.xer_out
+ if not (yield alu.n.data_o.xer_so.ok):
+ return
+ if xer_out or (oe and oe_ok):
res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
def get_xer_ov(res, alu, dec2):
- oe = yield dec2.e.oe.oe
- oe_ok = yield dec2.e.oe.ok
- if oe and oe_ok:
+ oe = yield dec2.e.do.oe.oe
+ oe_ok = yield dec2.e.do.oe.ok
+ xer_out = yield dec2.e.xer_out
+ if not (yield alu.n.data_o.xer_ov.ok):
+ return
+ if xer_out or (oe and oe_ok):
res['xer_ov'] = yield alu.n.data_o.xer_ov.data
def get_xer_ca(res, alu, dec2):
- cry_out = yield dec2.e.output_carry
- if cry_out:
+ cry_out = yield dec2.e.do.output_carry
+ xer_out = yield dec2.e.xer_out
+ if not (yield alu.n.data_o.xer_ca.ok):
+ return
+ if xer_out or (cry_out):
res['xer_ca'] = yield alu.n.data_o.xer_ca.data
def get_sim_int_o(res, sim, dec2):
spr_name = spr_dict[spr_num].SPR
res['fast1'] = sim.spr[spr_name].value
+ def get_wr_slow_spr1(res, sim, dec2):
+ ok = yield dec2.e.write_spr.ok
+ if ok:
+ spr_num = yield dec2.e.write_spr.data
+ spr_name = spr_dict[spr_num].SPR
+ res['spr1'] = sim.spr[spr_name].value
+
def get_wr_sim_xer_ca(res, sim, dec2):
- cry_out = yield dec2.e.output_carry
- if cry_out:
+ #if not (yield alu.n.data_o.xer_ca.ok):
+ # return
+ cry_out = yield dec2.e.do.output_carry
+ xer_out = yield dec2.e.xer_out
+ if cry_out or xer_out:
expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
res['xer_ca'] = expected_carry | (expected_carry32 << 1)
+ def get_wr_sim_xer_ov(res, sim, alu, dec2):
+ oe = yield dec2.e.do.oe.oe
+ oe_ok = yield dec2.e.do.oe.ok
+ xer_out = yield dec2.e.xer_out
+ print ("get_wr_sim_xer_ov", xer_out)
+ if not (yield alu.n.data_o.xer_ov.ok):
+ return
+ if xer_out or (oe and oe_ok):
+ expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
+ expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
+ res['xer_ov'] = expected_ov | (expected_ov32 << 1)
+
+ def get_wr_sim_xer_so(res, sim, alu, dec2):
+ oe = yield dec2.e.do.oe.oe
+ oe_ok = yield dec2.e.do.oe.ok
+ xer_out = yield dec2.e.xer_out
+ if not (yield alu.n.data_o.xer_so.ok):
+ return
+ if xer_out or (oe and oe_ok):
+ res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
+
def get_sim_xer_ov(res, sim, dec2):
- oe = yield dec2.e.oe.oe
- oe_ok = yield dec2.e.oe.ok
- if oe and oe_ok:
+ oe = yield dec2.e.do.oe.oe
+ oe_ok = yield dec2.e.do.oe.ok
+ xer_in = yield dec2.e.xer_in
+ print ("get_sim_xer_ov", xer_in)
+ if xer_in or (oe and oe_ok):
expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
res['xer_ov'] = expected_ov | (expected_ov32 << 1)
def get_sim_xer_so(res, sim, dec2):
- oe = yield dec2.e.oe.oe
- oe_ok = yield dec2.e.oe.ok
- if oe and oe_ok:
+ oe = yield dec2.e.do.oe.oe
+ oe_ok = yield dec2.e.do.oe.ok
+ xer_in = yield dec2.e.xer_in
+ if xer_in or (oe and oe_ok):
res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
+ def check_slow_spr1(dut, res, sim_o, msg):
+ if 'spr1' in res:
+ expected = sim_o['spr1']
+ alu_out = res['spr1']
+ print(f"expected {expected:x}, actual: {alu_out:x}")
+ dut.assertEqual(expected, alu_out, msg)
+
def check_fast_spr1(dut, res, sim_o, msg):
if 'fast1' in res:
expected = sim_o['fast1']
if 'o' in res:
expected = sim_o['o']
alu_out = res['o']
+ print(f"expected int sim {expected:x}, actual: {alu_out:x}")
+ dut.assertEqual(expected, alu_out, msg)
+
+ def check_msr(dut, res, sim_o, msg):
+ if 'msr' in res:
+ expected = sim_o['msr']
+ alu_out = res['msr']
print(f"expected {expected:x}, actual: {alu_out:x}")
dut.assertEqual(expected, alu_out, msg)
projects / soc.git / blobdiff