put set_msr and set_cia back in for now

[soc.git] / src / soc / fu / test / common.py

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index b07b3885899e82fabc1c275df511fab8d2d6f036..a4b9f0e8e7099360079fed7b6997a032cd91634d 100644 (file)
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -10,7 +10,9 @@ from soc.regfile.regfiles import FastRegs
 
 class TestCase:
     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
-                       msr=0):
+                       msr=0,
+                       do_sim=True,
+                       extra_break_addr=None):
 
         self.program = program
         self.name = name
@@ -26,6 +28,9 @@ class TestCase:
         self.cr = cr
         self.mem = mem
         self.msr = msr
+        self.do_sim = do_sim
+        self.extra_break_addr = extra_break_addr
+
 
 class ALUHelpers:
 
@@ -140,10 +145,12 @@ class ALUHelpers:
             yield alu.p.data_i.xer_so.eq(so)
 
     def set_msr(alu, dec2, inp):
+        print ("TODO: deprecate set_msr")
         if 'msr' in inp:
             yield alu.p.data_i.msr.eq(inp['msr'])
 
     def set_cia(alu, dec2, inp):
+        print ("TODO: deprecate set_cia")
         if 'cia' in inp:
             yield alu.p.data_i.cia.eq(inp['cia'])
 
@@ -376,7 +383,7 @@ class ALUHelpers:
         if 'o' in res:
             expected = sim_o['o']
             alu_out = res['o']
-            print(f"expected {expected:x}, actual: {alu_out:x}")
+            print(f"expected int sim {expected:x}, actual: {alu_out:x}")
             dut.assertEqual(expected, alu_out, msg)
 
     def check_msr(dut, res, sim_o, msg):