put set_msr and set_cia back in for now

[soc.git] / src / soc / fu / test / common.py

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index e41ee4b338262bd295970205793e4acfcd3053ce..a4b9f0e8e7099360079fed7b6997a032cd91634d 100644 (file)
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -10,7 +10,9 @@ from soc.regfile.regfiles import FastRegs
 
 class TestCase:
     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
-                       msr=0):
+                       msr=0,
+                       do_sim=True,
+                       extra_break_addr=None):
 
         self.program = program
         self.name = name
@@ -26,6 +28,9 @@ class TestCase:
         self.cr = cr
         self.mem = mem
         self.msr = msr
+        self.do_sim = do_sim
+        self.extra_break_addr = extra_break_addr
+
 
 class ALUHelpers:
 
@@ -93,7 +98,7 @@ class ALUHelpers:
             res['rc'] = sim.gpr(data).value
 
     def get_rd_sim_xer_ca(res, sim, dec2):
-        cry_in = yield dec2.e.input_carry
+        cry_in = yield dec2.e.do.input_carry
         xer_in = yield dec2.e.xer_in
         if xer_in or cry_in == CryIn.CA.value:
             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
@@ -112,9 +117,9 @@ class ALUHelpers:
         if 'rb' in inp:
             yield alu.p.data_i.rb.eq(inp['rb'])
         # If there's an immediate, set the B operand to that
-        imm_ok = yield dec2.e.imm_data.imm_ok
+        imm_ok = yield dec2.e.do.imm_data.imm_ok
         if imm_ok:
-            data2 = yield dec2.e.imm_data.imm
+            data2 = yield dec2.e.do.imm_data.imm
             yield alu.p.data_i.rb.eq(data2)
 
     def set_int_rc(alu, dec2, inp):
@@ -140,10 +145,12 @@ class ALUHelpers:
             yield alu.p.data_i.xer_so.eq(so)
 
     def set_msr(alu, dec2, inp):
+        print ("TODO: deprecate set_msr")
         if 'msr' in inp:
             yield alu.p.data_i.msr.eq(inp['msr'])
 
     def set_cia(alu, dec2, inp):
+        print ("TODO: deprecate set_cia")
         if 'cia' in inp:
             yield alu.p.data_i.cia.eq(inp['cia'])
 
@@ -230,22 +237,28 @@ class ALUHelpers:
             res['cr_a'] = yield alu.n.data_o.cr0.data
 
     def get_xer_so(res, alu, dec2):
-        oe = yield dec2.e.oe.oe
-        oe_ok = yield dec2.e.oe.ok
+        oe = yield dec2.e.do.oe.oe
+        oe_ok = yield dec2.e.do.oe.ok
         xer_out = yield dec2.e.xer_out
+        if not (yield alu.n.data_o.xer_so.ok):
+            return
         if xer_out or (oe and oe_ok):
             res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
 
     def get_xer_ov(res, alu, dec2):
-        oe = yield dec2.e.oe.oe
-        oe_ok = yield dec2.e.oe.ok
+        oe = yield dec2.e.do.oe.oe
+        oe_ok = yield dec2.e.do.oe.ok
         xer_out = yield dec2.e.xer_out
+        if not (yield alu.n.data_o.xer_ov.ok):
+            return
         if xer_out or (oe and oe_ok):
             res['xer_ov'] = yield alu.n.data_o.xer_ov.data
 
     def get_xer_ca(res, alu, dec2):
-        cry_out = yield dec2.e.output_carry
+        cry_out = yield dec2.e.do.output_carry
         xer_out = yield dec2.e.xer_out
+        if not (yield alu.n.data_o.xer_ca.ok):
+            return
         if xer_out or (cry_out):
             res['xer_ca'] = yield alu.n.data_o.xer_ca.data
 
@@ -291,15 +304,39 @@ class ALUHelpers:
             res['spr1'] = sim.spr[spr_name].value
 
     def get_wr_sim_xer_ca(res, sim, dec2):
-        cry_out = yield dec2.e.output_carry
-        if cry_out:
+        #if not (yield alu.n.data_o.xer_ca.ok):
+        #    return
+        cry_out = yield dec2.e.do.output_carry
+        xer_out = yield dec2.e.xer_out
+        if cry_out or xer_out:
             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 
+    def get_wr_sim_xer_ov(res, sim, alu, dec2):
+        oe = yield dec2.e.do.oe.oe
+        oe_ok = yield dec2.e.do.oe.ok
+        xer_out = yield dec2.e.xer_out
+        print ("get_wr_sim_xer_ov", xer_out)
+        if not (yield alu.n.data_o.xer_ov.ok):
+            return
+        if xer_out or (oe and oe_ok):
+            expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
+            expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
+            res['xer_ov'] = expected_ov | (expected_ov32 << 1)
+
+    def get_wr_sim_xer_so(res, sim, alu, dec2):
+        oe = yield dec2.e.do.oe.oe
+        oe_ok = yield dec2.e.do.oe.ok
+        xer_out = yield dec2.e.xer_out
+        if not (yield alu.n.data_o.xer_so.ok):
+            return
+        if xer_out or (oe and oe_ok):
+            res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
+
     def get_sim_xer_ov(res, sim, dec2):
-        oe = yield dec2.e.oe.oe
-        oe_ok = yield dec2.e.oe.ok
+        oe = yield dec2.e.do.oe.oe
+        oe_ok = yield dec2.e.do.oe.ok
         xer_in = yield dec2.e.xer_in
         print ("get_sim_xer_ov", xer_in)
         if xer_in or (oe and oe_ok):
@@ -308,8 +345,8 @@ class ALUHelpers:
             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 
     def get_sim_xer_so(res, sim, dec2):
-        oe = yield dec2.e.oe.oe
-        oe_ok = yield dec2.e.oe.ok
+        oe = yield dec2.e.do.oe.oe
+        oe_ok = yield dec2.e.do.oe.ok
         xer_in = yield dec2.e.xer_in
         if xer_in or (oe and oe_ok):
             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
@@ -346,6 +383,13 @@ class ALUHelpers:
         if 'o' in res:
             expected = sim_o['o']
             alu_out = res['o']
+            print(f"expected int sim {expected:x}, actual: {alu_out:x}")
+            dut.assertEqual(expected, alu_out, msg)
+
+    def check_msr(dut, res, sim_o, msg):
+        if 'msr' in res:
+            expected = sim_o['msr']
+            alu_out = res['msr']
             print(f"expected {expected:x}, actual: {alu_out:x}")
             dut.assertEqual(expected, alu_out, msg)