more openpower-isa conversion

[soc.git] / src / soc / fu / trap / main_stage.py

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 5b272e63c44a3a85568a24f7d86561d52b44c797..afc2e677dd84fa16c88505dcde051fce23ed88b4 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -20,7 +20,7 @@ from soc.experiment.mem_types import LDSTException
 from openpower.decoder.power_fields import DecodeFields
 from openpower.decoder.power_fieldsn import SignalBitRange
 
-from soc.consts import MSR, PI, TT, field, field_slice
+from openpower.consts import MSR, PI, TT, field, field_slice
 
 
 def msr_copy(msr_o, msr_i, zero_me=True):