from nmutil.extend import exts
from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
from soc.fu.branch.main_stage import br_ext
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
from soc.decoder.power_fields import DecodeFields
from soc.decoder.power_fieldsn import SignalBitRange
-from soc.decoder.power_decoder2 import (TT_FP, TT_PRIV, TT_TRAP, TT_ADDR,
- TT_ILLEG)
-from soc.consts import MSR, PI
+from soc.consts import MSR, PI, TT
def msr_copy(msr_o, msr_i, zero_me=True):
comb += msr_copy(srr1_o.data, msr_i) # old MSR
comb += srr1_o.ok.eq(1)
+ def msr_exception(self, m, trap_addr):
+ """msr_exception - sets bits in MSR specific to an exception.
+ the full list of what needs to be done is given in V3.0B
+ Book III Section 6.5 p1063 however it turns out that for the
+ majority of cases (microwatt showing the way, here), all these
+ bits are all set by all (implemented) interrupt types. this
+ may change in the future, hence the (unused) trap_addr argument
+ """
+ comb = m.d.comb
+ msr_i, msr_o = self.i.msr, self.o.msr
+ comb += msr_o.data.eq(msr_i) # copy msr, first, then modify
+ comb += msr_o.data[MSR.SF].eq(1)
+ comb += msr_o.data[MSR.EE].eq(0)
+ comb += msr_o.data[MSR.PR].eq(0)
+ comb += msr_o.data[MSR.IR].eq(0)
+ comb += msr_o.data[MSR.DR].eq(0)
+ comb += msr_o.data[MSR.RI].eq(0)
+ comb += msr_o.data[MSR.LE].eq(1)
+ comb += msr_o.ok.eq(1)
+
def ispec(self):
return TrapInputData(self.pspec)
# TODO: some #defines for the bits n stuff.
with m.Switch(op.insn_type):
#### trap ####
- with m.Case(InternalOp.OP_TRAP):
+ with m.Case(MicrOp.OP_TRAP):
# trap instructions (tw, twi, td, tdi)
with m.If(should_trap):
# generate trap-type program interrupt
self.trap(m, trapaddr<<4, cia_i)
with m.If(traptype == 0):
- # say trap occurred (see 3.0B Book III 7.5.9)
+ # say trap occurred (see 3.0B Book III 6.5.9 p1074-6)
comb += srr1_o.data[PI.TRAP].eq(1)
- with m.If(traptype & TT_PRIV):
+ with m.If(traptype & TT.PRIV):
comb += srr1_o.data[PI.PRIV].eq(1)
- with m.If(traptype & TT_FP):
+ with m.If(traptype & TT.FP):
comb += srr1_o.data[PI.FP].eq(1)
- with m.If(traptype & TT_ADDR):
+ with m.If(traptype & TT.ADDR):
comb += srr1_o.data[PI.ADR].eq(1)
- with m.If(traptype & TT_ILLEG):
+ with m.If(traptype & TT.ILLEG):
comb += srr1_o.data[PI.ILLEG].eq(1)
+ comb += srr1_o.ok.eq(1)
+
+ # when SRR1 is written to, update MSR bits
+ self.msr_exception(m, trapaddr)
# move to MSR
- with m.Case(InternalOp.OP_MTMSRD, InternalOp.OP_MTMSR):
+ with m.Case(MicrOp.OP_MTMSRD, MicrOp.OP_MTMSR):
L = self.fields.FormX.L[0:-1] # X-Form field L
# start with copy of msr
comb += msr_o.eq(msr_i)
with m.Else():
# Architecture says to leave out bits 3 (HV), 51 (ME)
# and 63 (LE) (IBM bit numbering)
- for stt, end in [(1,12), (13, 60), (61, 64)]:
- comb += msr_o.data[stt:end].eq(a_i[stt:end])
+ with m.If(op.insn_type == MicrOp.OP_MTMSRD):
+ for stt, end in [(1,12), (13, 60), (61, 64)]:
+ comb += msr_o.data[stt:end].eq(a_i[stt:end])
+ with m.Else():
+ # mtmsr - 32-bit, only room for bottom 32 LSB flags
+ for stt, end in [(1,12), (13, 32)]:
+ comb += msr_o.data[stt:end].eq(a_i[stt:end])
msr_check_pr(m, msr_o.data)
comb += msr_o.ok.eq(1)
# move from MSR
- with m.Case(InternalOp.OP_MFMSR):
+ with m.Case(MicrOp.OP_MFMSR):
# TODO: some of the bits need zeroing? apparently not
comb += o.data.eq(msr_i)
comb += o.ok.eq(1)
- with m.Case(InternalOp.OP_RFID):
+ with m.Case(MicrOp.OP_RFID):
# XXX f_out.virt_mode <= b_in(MSR.IR) or b_in(MSR.PR);
# XXX f_out.priv_mode <= not b_in(MSR.PR);
# return addr was in srr0
comb += nia_o.data.eq(br_ext(srr0_i[2:]))
comb += nia_o.ok.eq(1)
- # MSR was in srr1
+
+ # MSR was in srr1: copy it over, however *caveats below*
comb += msr_copy(msr_o.data, srr1_i, zero_me=False) # don't zero
+
+ # check problem state
msr_check_pr(m, msr_o.data)
- # hypervisor stuff
- comb += msr_o.data[MSR.HV].eq(msr_i[MSR.HV] & srr1_i[MSR.HV])
- comb += msr_o.data[MSR.ME].eq((msr_i[MSR.HV] & srr1_i[MSR.HV]) |
- (~msr_i[MSR.HV] & srr1_i[MSR.HV]))
- # don't understand but it's in the spec
- with m.If((msr_i[63-31:63-29] != Const(0b010, 3)) |
- (srr1_i[63-31:63-29] != Const(0b000, 3))):
- comb += msr_o.data[63-31:63-29].eq(srr1_i[63-31:63-29])
- with m.Else():
- comb += msr_o.data[63-31:63-29].eq(msr_i[63-31:63-29])
+ # hypervisor stuff. here: bits 3 (HV) and 51 (ME) were
+ # copied over by msr_copy but if HV was not set we need
+ # the *original* (msr_i) bits
+ with m.If(~msr_i[MSR.HV]):
+ comb += msr_o.data[MSR.HV].eq(msr_i[MSR.HV])
+ comb += msr_o.data[MSR.ME].eq(msr_i[MSR.ME])
+
+ # don't understand but it's in the spec. again: bits 32-34
+ # are copied from srr1_i and need *restoring* to msr_i
+ bits = slice(63-31,63-29+1) # bits 29, 30, 31 (Power notation)
+ with m.If((msr_i[bits] == Const(0b010, 3)) &
+ (srr1_i[bits] == Const(0b000, 3))):
+ comb += msr_o.data[bits].eq(msr_i[bits])
+
comb += msr_o.ok.eq(1)
# OP_SC
- with m.Case(InternalOp.OP_SC):
- # TODO: scv must generate illegal instruction. this is
- # the decoder's job, not ours, here.
+ with m.Case(MicrOp.OP_SC):
+ # scv is not covered here. currently an illegal instruction.
+ # raising "illegal" is the decoder's job, not ours, here.
# jump to the trap address, return at cia+4
self.trap(m, 0xc00, cia_i+4)
+ # and update several MSR bits
+ self.msr_exception(m, 0xc00)
+
# TODO (later)
- #with m.Case(InternalOp.OP_ADDPCIS):
+ #with m.Case(MicrOp.OP_ADDPCIS):
# pass
comb += self.o.ctx.eq(self.i.ctx)
projects / soc.git / blobdiff