"""Trap Pipeline
+Deals with td/tw/tdi/twi as well as mfmsr/mtmsr, sc and rfid. addpcis TODO.
+Also used generally for interrupts (as a micro-coding mechanism) by
+actually modifying the decoded instruction in PowerDecode2.
+
* https://bugs.libre-soc.org/show_bug.cgi?id=325
* https://bugs.libre-soc.org/show_bug.cgi?id=344
* https://libre-soc.org/openpower/isa/fixedtrap/
from nmutil.extend import exts
from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
from soc.fu.branch.main_stage import br_ext
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
from soc.decoder.power_fields import DecodeFields
from soc.decoder.power_fieldsn import SignalBitRange
-from soc.decoder.power_decoder2 import (TT_FP, TT_PRIV, TT_TRAP, TT_ADDR)
-
-# Listed in V3.0B Book III Chap 4.2.1
-# MSR bit numbers
-MSR_SF = (63 - 0) # Sixty-Four bit mode
-MSR_HV = (63 - 3) # Hypervisor state
-MSR_S = (63 - 41) # Secure state
-MSR_EE = (63 - 48) # External interrupt Enable
-MSR_PR = (63 - 49) # PRoblem state
-MSR_FP = (63 - 50) # FP available
-MSR_ME = (63 - 51) # Machine Check int enable
-MSR_IR = (63 - 58) # Instruction Relocation
-MSR_DR = (63 - 59) # Data Relocation
-MSR_PMM = (63 - 60) # Performance Monitor Mark
-MSR_RI = (63 - 62) # Recoverable Interrupt
-MSR_LE = (63 - 63) # Little Endian
-
-# Listed in V3.0B Book III 7.5.9 "Program Interrupt"
-
-# note that these correspond to trap_input_record.traptype bits 0,1,2,3
-# (TODO: add more?)
-
-PI_FP = (63 - 43) # 1 if FP exception
-PI_PRIV = (63 - 45) # 1 if privileged interrupt
-PI_TRAP = (63 - 46) # 1 if exception is "trap" type
-PI_ADR = (63 - 47) # 0 if SRR0 = address of instruction causing exception
+from soc.consts import MSR, PI, TT
def msr_copy(msr_o, msr_i, zero_me=True):
- """
- -- ISA says this:
- -- Defined MSR bits are classified as either full func-
- -- tion or partial function. Full function MSR bits are
- -- saved in SRR1 or HSRR1 when an interrupt other
- -- than a System Call Vectored interrupt occurs and
- -- restored by rfscv, rfid, or hrfid, while partial func-
- -- tion MSR bits are not saved or restored.
- -- Full function MSR bits lie in the range 0:32, 37:41, and
- -- 48:63, and partial function MSR bits lie in the range
- -- 33:36 and 42:47. (Note this is IBM bit numbering).
- msr_out := (others => '0');
- msr_out(63 downto 31) := msr(63 downto 31);
- msr_out(26 downto 22) := msr(26 downto 22);
- msr_out(15 downto 0) := msr(15 downto 0);
+ """msr_copy
+ ISA says this:
+ Defined MSR bits are classified as either full func tion or partial
+ function. Full function MSR bits are saved in SRR1 or HSRR1 when
+ an interrupt other than a System Call Vectored interrupt occurs and
+ restored by rfscv, rfid, or hrfid, while partial function MSR bits
+ are not saved or restored. Full function MSR bits lie in the range
+ 0:32, 37:41, and 48:63, and partial function MSR bits lie in the
+ range 33:36 and 42:47. (Note this is IBM bit numbering).
"""
l = []
if zero_me:
"""msr_check_pr: checks "problem state"
"""
comb = m.d.comb
- with m.If(msr[MSR_PR]):
- comb += msr[MSR_EE].eq(1) # set external interrupt bit
- comb += msr[MSR_IR].eq(1) # set instruction relocation bit
- comb += msr[MSR_DR].eq(1) # set data relocation bit
+ with m.If(msr[MSR.PR]):
+ comb += msr[MSR.EE].eq(1) # set external interrupt bit
+ comb += msr[MSR.IR].eq(1) # set instruction relocation bit
+ comb += msr[MSR.DR].eq(1) # set data relocation bit
class TrapMainStage(PipeModBase):
self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
self.fields.create_specs()
- def trap(self, m, return_addr, trap_addr):
- """trap """ # TODO add descriptive docstring
+ def trap(self, m, trap_addr, return_addr):
+ """trap. sets new PC, stores MSR and old PC in SRR1 and SRR0
+ """
comb = m.d.comb
+ msr_i = self.i.msr
nia_o, srr0_o, srr1_o = self.o.nia, self.o.srr0, self.o.srr1
# trap address
comb += msr_copy(srr1_o.data, msr_i) # old MSR
comb += srr1_o.ok.eq(1)
+ def msr_exception(self, m, trap_addr):
+ """msr_exception - sets bits in MSR specific to an exception.
+ the full list of what needs to be done is given in V3.0B
+ Book III Section 6.5 p1063 however it turns out that for the
+ majority of cases (microwatt showing the way, here), all these
+ bits are all set by all (implemented) interrupt types. this
+ may change in the future, hence the (unused) trap_addr argument
+ """
+ comb = m.d.comb
+ msr_i, msr_o = self.i.msr, self.o.msr
+ comb += msr_o.data.eq(msr_i) # copy msr, first, then modify
+ comb += msr_o.data[MSR.SF].eq(1)
+ comb += msr_o.data[MSR.EE].eq(0)
+ comb += msr_o.data[MSR.PR].eq(0)
+ comb += msr_o.data[MSR.IR].eq(0)
+ comb += msr_o.data[MSR.DR].eq(0)
+ comb += msr_o.data[MSR.RI].eq(0)
+ comb += msr_o.data[MSR.LE].eq(1)
+ comb += msr_o.ok.eq(1)
+
def ispec(self):
return TrapInputData(self.pspec)
# convenience variables
a_i, b_i, cia_i, msr_i = self.i.a, self.i.b, self.i.cia, self.i.msr
+ srr0_i, srr1_i = self.i.srr0, self.i.srr1
o, msr_o, nia_o = self.o.o, self.o.msr, self.o.nia
srr0_o, srr1_o = self.o.srr0, self.o.srr1
traptype, trapaddr = op.traptype, op.trapaddr
comb += should_trap.eq((trap_bits & to).any() | traptype.any())
# TODO: some #defines for the bits n stuff.
- with m.Switch(op):
+ with m.Switch(op.insn_type):
#### trap ####
- with m.Case(InternalOp.OP_TRAP):
+ with m.Case(MicrOp.OP_TRAP):
# trap instructions (tw, twi, td, tdi)
with m.If(should_trap):
# generate trap-type program interrupt
- self.trap(trapaddr<<4, cia_i)
+ self.trap(m, trapaddr<<4, cia_i)
with m.If(traptype == 0):
- # say trap occurred (see 3.0B Book III 7.5.9)
- comb += srr1_o.data[PI_TRAP].eq(1)
- with m.If(traptype & TT_PRIV):
- comb += srr1_o.data[PI_PRIV].eq(1)
- with m.If(traptype & TT_FP):
- comb += srr1_o.data[PI_FP].eq(1)
- with m.If(traptype & TT_ADDR):
- comb += srr1_o.data[PI_ADDR].eq(1)
+ # say trap occurred (see 3.0B Book III 6.5.9 p1074-6)
+ comb += srr1_o.data[PI.TRAP].eq(1)
+ with m.If(traptype & TT.PRIV):
+ comb += srr1_o.data[PI.PRIV].eq(1)
+ with m.If(traptype & TT.FP):
+ comb += srr1_o.data[PI.FP].eq(1)
+ with m.If(traptype & TT.ADDR):
+ comb += srr1_o.data[PI.ADR].eq(1)
+ with m.If(traptype & TT.ILLEG):
+ comb += srr1_o.data[PI.ILLEG].eq(1)
+ comb += srr1_o.ok.eq(1)
+
+ # when SRR1 is written to, update MSR bits
+ self.msr_exception(m, trapaddr)
# move to MSR
- with m.Case(InternalOp.OP_MTMSR):
+ with m.Case(MicrOp.OP_MTMSRD, MicrOp.OP_MTMSR):
L = self.fields.FormX.L[0:-1] # X-Form field L
+ # start with copy of msr
+ comb += msr_o.eq(msr_i)
with m.If(L):
- # just update EE and RI
- comb += msr_o.data[MSR_EE].eq(a_i[MSR_EE])
- comb += msr_o.data[MSR_RI].eq(a_i[MSR_RI])
+ # just update RI..EE
+ comb += msr_o.data[MSR.RI].eq(a_i[MSR.RI])
+ comb += msr_o.data[MSR.EE].eq(a_i[MSR.EE])
with m.Else():
# Architecture says to leave out bits 3 (HV), 51 (ME)
# and 63 (LE) (IBM bit numbering)
- for stt, end in [(1,12), (13, 60), (61, 64)]:
- comb += msr_o.data[stt:end].eq(a_i[stt:end])
+ with m.If(op.insn_type == MicrOp.OP_MTMSRD):
+ for stt, end in [(1,12), (13, 60), (61, 64)]:
+ comb += msr_o.data[stt:end].eq(a_i[stt:end])
+ with m.Else():
+ # mtmsr - 32-bit, only room for bottom 32 LSB flags
+ for stt, end in [(1,12), (13, 32)]:
+ comb += msr_o.data[stt:end].eq(a_i[stt:end])
msr_check_pr(m, msr_o.data)
comb += msr_o.ok.eq(1)
# move from MSR
- with m.Case(InternalOp.OP_MFMSR):
+ with m.Case(MicrOp.OP_MFMSR):
# TODO: some of the bits need zeroing? apparently not
comb += o.data.eq(msr_i)
comb += o.ok.eq(1)
- with m.Case(InternalOp.OP_RFID):
- # XXX f_out.virt_mode <= b_in(MSR_IR) or b_in(MSR_PR);
- # XXX f_out.priv_mode <= not b_in(MSR_PR);
+ with m.Case(MicrOp.OP_RFID):
+ # XXX f_out.virt_mode <= b_in(MSR.IR) or b_in(MSR.PR);
+ # XXX f_out.priv_mode <= not b_in(MSR.PR);
# return addr was in srr0
comb += nia_o.data.eq(br_ext(srr0_i[2:]))
comb += nia_o.ok.eq(1)
- # MSR was in srr1
+
+ # MSR was in srr1: copy it over, however *caveats below*
comb += msr_copy(msr_o.data, srr1_i, zero_me=False) # don't zero
+
+ # check problem state
msr_check_pr(m, msr_o.data)
+
+ # hypervisor stuff. here: bits 3 (HV) and 51 (ME) were
+ # copied over by msr_copy but if HV was not set we need
+ # the *original* (msr_i) bits
+ with m.If(~msr_i[MSR.HV]):
+ comb += msr_o.data[MSR.HV].eq(msr_i[MSR.HV])
+ comb += msr_o.data[MSR.ME].eq(msr_i[MSR.ME])
+
+ # don't understand but it's in the spec. again: bits 32-34
+ # are copied from srr1_i and need *restoring* to msr_i
+ bits = slice(63-31,63-29+1) # bits 29, 30, 31 (Power notation)
+ with m.If((msr_i[bits] == Const(0b010, 3)) &
+ (srr1_i[bits] == Const(0b000, 3))):
+ comb += msr_o.data[bits].eq(msr_i[bits])
+
comb += msr_o.ok.eq(1)
- with m.Case(InternalOp.OP_SC):
- # TODO: scv must generate illegal instruction. this is
- # the decoder's job, not ours, here.
+ # OP_SC
+ with m.Case(MicrOp.OP_SC):
+ # scv is not covered here. currently an illegal instruction.
+ # raising "illegal" is the decoder's job, not ours, here.
# jump to the trap address, return at cia+4
- self.trap(0xc00, cia_i+4)
+ self.trap(m, 0xc00, cia_i+4)
+
+ # and update several MSR bits
+ self.msr_exception(m, 0xc00)
# TODO (later)
- #with m.Case(InternalOp.OP_ADDPCIS):
+ #with m.Case(MicrOp.OP_ADDPCIS):
# pass
comb += self.o.ctx.eq(self.i.ctx)
projects / soc.git / blobdiff