add SVSTATE (SVSRR0) to TRAP pipeline

[soc.git] / src / soc / fu / trap / trap_input_record.py

diff --git a/src/soc/fu/trap/trap_input_record.py b/src/soc/fu/trap/trap_input_record.py
index 7bdae248e94a833a1d77c673b03f9b7ffddd62c7..4d3d66e8d8980af2ea55b6a32ae7b80d90ba0aba 100644 (file)
--- a/src/soc/fu/trap/trap_input_record.py
+++ b/src/soc/fu/trap/trap_input_record.py
@@ -14,8 +14,9 @@ class CompTrapOpSubset(CompOpSubsetBase):
         layout = [('insn_type', MicrOp),
                   ('fn_unit', Function),
                   ('insn', 32),
-                  ('msr', 64), # from core.state
-                  ('cia', 64), # likewise
+                  ('msr', 64),     # from core.state
+                  ('cia', 64),     # likewise
+                  ('svstate', 32), # likewise
                   ('is_32bit', 1),
                   ('traptype', TT.size), # see trap main_stage.py, PowerDecoder2
                   ('trapaddr', 13),