hook up MSR into MMU (TODO, use a lot less bits)

[soc.git] / src / soc / fu / trap / trap_input_record.py

diff --git a/src/soc/fu/trap/trap_input_record.py b/src/soc/fu/trap/trap_input_record.py
index 5b86693fd7d95d9b2bd59a316fcb3618480a3e85..7bdae248e94a833a1d77c673b03f9b7ffddd62c7 100644 (file)
--- a/src/soc/fu/trap/trap_input_record.py
+++ b/src/soc/fu/trap/trap_input_record.py
@@ -14,7 +14,7 @@ class CompTrapOpSubset(CompOpSubsetBase):
         layout = [('insn_type', MicrOp),
                   ('fn_unit', Function),
                   ('insn', 32),
-                  ('msr', 64), # TODO: "state" in separate Record
+                  ('msr', 64), # from core.state
                   ('cia', 64), # likewise
                   ('is_32bit', 1),
                   ('traptype', TT.size), # see trap main_stage.py, PowerDecoder2