Allow the formal engine to perform a same-cycle result in the ALU

[soc.git] / src / soc / fu / trap / trap_input_record.py

diff --git a/src/soc/fu/trap/trap_input_record.py b/src/soc/fu/trap/trap_input_record.py
index 5b86693fd7d95d9b2bd59a316fcb3618480a3e85..107bc0f4c7e8d5f5f0275f7062c0681cf531eb2c 100644 (file)
--- a/src/soc/fu/trap/trap_input_record.py
+++ b/src/soc/fu/trap/trap_input_record.py
@@ -14,12 +14,13 @@ class CompTrapOpSubset(CompOpSubsetBase):
         layout = [('insn_type', MicrOp),
                   ('fn_unit', Function),
                   ('insn', 32),
-                  ('msr', 64), # TODO: "state" in separate Record
-                  ('cia', 64), # likewise
+                  ('msr', 64),     # from core.state
+                  ('cia', 64),     # likewise
+                  ('svstate', 64), # likewise
                   ('is_32bit', 1),
                   ('traptype', TT.size), # see trap main_stage.py, PowerDecoder2
                   ('trapaddr', 13),
-                  ('ldst_exc', len(LDSTException._exc_types)),
+                  ('ldst_exc', LDSTException.length), # blech
                   ]
 
         super().__init__(layout, name=name)