-from nmigen.hdl.rec import Record, Layout
+from soc.fu.base_input_record import CompOpSubsetBase
+from openpower.decoder.power_enums import (MicrOp, Function)
+from openpower.consts import TT
+from soc.experiment.mem_types import LDSTException
-from soc.decoder.power_enums import (InternalOp, Function)
-
-
-class CompTrapOpSubset(Record):
+class CompTrapOpSubset(CompOpSubsetBase):
"""CompTrapOpSubset
a copy of the relevant subset information from Decode2Execute1Type
grab subsets.
"""
def __init__(self, name=None):
- layout = (('insn_type', InternalOp),
+ layout = [('insn_type', MicrOp),
('fn_unit', Function),
('insn', 32),
+ ('msr', 64), # from core.state
+ ('cia', 64), # likewise
+ ('svstate', 64), # likewise
('is_32bit', 1),
- ('traptype', 5), # see trap main_stage.py and PowerDecoder2
+ ('traptype', TT.size), # see trap main_stage.py, PowerDecoder2
('trapaddr', 13),
- )
-
- Record.__init__(self, Layout(layout), name=name)
-
- # grrr. Record does not have kwargs
- self.insn_type.reset_less = True
- self.insn.reset_less = True
- self.fn_unit.reset_less = True
- self.is_32bit.reset_less = True
- self.traptype.reset_less = True
- self.trapaddr.reset_less = True
+ ('ldst_exc', LDSTException.length), # blech
+ ]
- def eq_from_execute1(self, other):
- """ use this to copy in from Decode2Execute1Type
- """
- res = []
- for fname, sig in self.fields.items():
- eqfrom = other.do.fields[fname]
- res.append(sig.eq(eqfrom))
- return res
+ super().__init__(layout, name=name)
- def ports(self):
- return [self.insn_type,
- self.insn,
- self.fn_unit,
- self.is_32bit,
- self.traptype,
- self.trapaddr,
- ]