Allow the formal engine to perform a same-cycle result in the ALU

[soc.git] / src / soc / fu / trap / trap_input_record.py

diff --git a/src/soc/fu/trap/trap_input_record.py b/src/soc/fu/trap/trap_input_record.py
index f7613790058fc9d5146a2ac3caa1206dcf96f40c..107bc0f4c7e8d5f5f0275f7062c0681cf531eb2c 100644 (file)
--- a/src/soc/fu/trap/trap_input_record.py
+++ b/src/soc/fu/trap/trap_input_record.py
@@ -1,6 +1,7 @@
 from soc.fu.base_input_record import CompOpSubsetBase
-from soc.decoder.power_enums import (MicrOp, Function)
-
+from openpower.decoder.power_enums import (MicrOp, Function)
+from openpower.consts import TT
+from soc.experiment.mem_types import LDSTException
 
 class CompTrapOpSubset(CompOpSubsetBase):
     """CompTrapOpSubset
@@ -10,15 +11,17 @@ class CompTrapOpSubset(CompOpSubsetBase):
     grab subsets.
     """
     def __init__(self, name=None):
-        layout = (('insn_type', MicrOp),
+        layout = [('insn_type', MicrOp),
                   ('fn_unit', Function),
                   ('insn', 32),
-                  ('msr', 64), # TODO: "state" in separate Record
-                  ('cia', 64), # likewise
+                  ('msr', 64),     # from core.state
+                  ('cia', 64),     # likewise
+                  ('svstate', 64), # likewise
                   ('is_32bit', 1),
-                  ('traptype', 5), # see trap main_stage.py and PowerDecoder2
+                  ('traptype', TT.size), # see trap main_stage.py, PowerDecoder2
                   ('trapaddr', 13),
-                  )
+                  ('ldst_exc', LDSTException.length), # blech
+                  ]
 
         super().__init__(layout, name=name)