reduce clkcsel ls180 width (2 pins), rename pll_18 signal

[soc.git] / src / soc / litex / florent / libresoc / core.py

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index b01c5fc8a7811db043d47b6e6a061d88ba107bd6..1c5211067ad75d53d08e4fbd3e3cbda5c31e3929 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -240,9 +240,11 @@ class LibreSoC(CPU):
         # add clock select, pll output
         if variant == "ls180":
             self.pll_18_o = Signal()
-            self.clk_sel = Signal(3)
+            self.clk_sel = Signal(2)
+            self.pll_lck_o = Signal()
             self.cpu_params['i_clk_sel_i'] = self.clk_sel
             self.cpu_params['o_pll_18_o'] = self.pll_18_o
+            self.cpu_params['o_pll_lck_o'] = self.pll_lck_o
 
         # add wishbone buses to cpu params
         self.cpu_params.update(make_wb_bus("ibus", ibus))