remove io_in/out now it is not needed for niolib

[soc.git] / src / soc / litex / florent / libresoc / core.py

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 38c8d008deaebbc214d4bb37ddd7f89c7934472b..370f9cdc2fb30cf518d48a87d3d066cbbb4eb28e 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -13,7 +13,9 @@ from libresoc.ls180 import io
 from litex.build.generic_platform import ConstraintManager
 
 
-CPU_VARIANTS = ["standard", "standard32", "standardjtag", "ls180"]
+CPU_VARIANTS = ["standard", "standard32", "standardjtag",
+                "standardjtagtestgpio", "ls180",
+                "standardjtagnoirq"]
 
 
 def make_wb_bus(prefix, obj, simple=False):
@@ -36,6 +38,7 @@ def make_wb_slave(prefix, obj):
     return res
 
 def make_pad(res, dirn, name, suffix, cpup, iop):
+    print ("make pad", dirn, name, suffix, cpup, iop)
     cpud, iod = ('i', 'o') if dirn else ('o', 'i')
     res['%s_%s__core__%s' % (cpud, name, suffix)] = cpup
     res['%s_%s__pad__%s' % (iod, name, suffix)] = iop
@@ -50,19 +53,33 @@ def get_field(rec, name):
 def make_jtag_ioconn(res, pin, cpupads, iopads):
     (fn, pin, iotype, pin_name, scan_idx) = pin
     #serial_tx__core__o, serial_rx__pad__i,
+    # special-case sdram_clock
+    if pin == 'clock' and fn == 'sdr':
+        cpu = cpupads['sdram_clock']
+        io = iopads['sdram_clock']
+    else:
+        cpu = cpupads[fn]
+        io = iopads[fn]
     print ("cpupads", cpupads)
     print ("iopads", iopads)
     print ("pin", fn, pin, iotype, pin_name)
-    cpu = cpupads[fn]
-    io = iopads[fn]
     print ("cpu fn", cpu)
     print ("io fn", io)
-    sigs = []
-
     name = "%s_%s" % (fn, pin)
+    print ("name", name)
+    sigs = []
 
     if iotype in (IOType.In, IOType.Out):
-        if pin.isdigit():
+        ps = pin.split("_")
+        if pin == 'clock' and fn == 'sdr':
+            cpup = cpu
+            iop = io
+        elif len(ps) == 2 and ps[-1].isdigit():
+            pin, idx = ps
+            idx = int(idx)
+            cpup = getattr(cpu, pin)[idx]
+            iop = getattr(io, pin)[idx]
+        elif pin.isdigit():
             idx = int(pin)
             cpup = cpu[idx]
             iop = io[idx]
@@ -83,13 +100,19 @@ def make_jtag_ioconn(res, pin, cpupads, iopads):
     elif iotype == IOType.InTriOut:
         if fn == 'gpio': # sigh decode GPIO special-case
             idx = int(pin[1:])
+            oe_idx = idx
+        elif fn == 'sdr': # sigh
+            idx = int(pin.split('_')[-1])
+            oe_idx = 0
         else:
             idx = 0
+            oe_idx = 0
+        print ("gpio tri", fn, pin, iotype, pin_name, scan_idx, idx)
         cpup, iop = get_field(cpu, "i")[idx], get_field(io, "i")[idx]
         make_pad(res, False, name, "i", cpup, iop)
         cpup, iop = get_field(cpu, "o")[idx], get_field(io, "o")[idx]
         make_pad(res, True, name, "o", cpup, iop)
-        cpup, iop = get_field(cpu, "oe")[idx], get_field(io, "oe")[idx]
+        cpup, iop = get_field(cpu, "oe")[oe_idx], get_field(io, "oe")[oe_idx]
         make_pad(res, True, name, "oe", cpup, iop)
 
     if iotype in (IOType.In, IOType.InTriOut):
@@ -134,7 +157,11 @@ class LibreSoC(CPU):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
-        self.interrupt    = Signal(16)
+
+        irq_en = "noirq" not in variant
+
+        if irq_en:
+            self.interrupt    = Signal(16)
 
         if variant == "standard32":
             self.data_width           = 32
@@ -149,7 +176,7 @@ class LibreSoC(CPU):
 
         jtag_en = ('jtag' in variant) or variant == 'ls180'
 
-        if variant != "ls180":
+        if "testgpio" in variant:
             self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
         if jtag_en:
             self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
@@ -185,11 +212,11 @@ class LibreSoC(CPU):
             o_busy_o           = Signal(),   # not connected
             o_memerr_o         = Signal(),   # not connected
             o_pc_o             = Signal(64), # not connected
+        )
 
+        if irq_en:
             # interrupts
-            i_int_level_i      = self.interrupt,
-
-        )
+            self.cpu_params['i_int_level_i'] = self.interrupt
 
         if jtag_en:
             self.cpu_params.update(dict(
@@ -216,13 +243,13 @@ class LibreSoC(CPU):
             self.clk_sel = Signal(3)
             self.cpu_params['i_clk_sel_i'] = self.clk_sel
             self.cpu_params['o_pll_48_o'] = self.pll_48_o
-    
+
         # add wishbone buses to cpu params
         self.cpu_params.update(make_wb_bus("ibus", ibus))
         self.cpu_params.update(make_wb_bus("dbus", dbus))
         self.cpu_params.update(make_wb_slave("ics_wb", ics))
         self.cpu_params.update(make_wb_slave("icp_wb", icp))
-        if variant != "ls180":
+        if "testgpio" in variant:
             self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
         if jtag_en:
             self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
@@ -236,7 +263,7 @@ class LibreSoC(CPU):
             iopads = {}
             litexmap = {}
             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
-                      'pwm', 'sd0'}#, 'sdr'}
+                      'pwm', 'sd0', 'sdr'}
             for periph in subset:
                 origperiph = periph
                 num = None
@@ -248,6 +275,8 @@ class LibreSoC(CPU):
                         periph, num = 'spimaster', None
                     else:
                         periph, num = 'spisdcard', None
+                elif periph == 'sdr':
+                    periph = 'sdram'
                 elif periph == 'mtwi':
                     periph = 'i2c'
                 elif periph == 'sd':
@@ -255,6 +284,12 @@ class LibreSoC(CPU):
                 litexmap[origperiph] = (periph, num)
                 self.cpupads[origperiph] = platform.request(periph, num)
                 iopads[origperiph] = self.pad_cm.request(periph, num)
+                if periph == 'sdram':
+                    # special-case sdram clock
+                    ck = platform.request("sdram_clock")
+                    self.cpupads['sdram_clock'] = ck
+                    ck = self.pad_cm.request("sdram_clock")
+                    iopads['sdram_clock'] = ck
 
             pinset = get_pinspecs(subset=subset)
             p = Pins(pinset)