from litex.build.generic_platform import ConstraintManager
-CPU_VARIANTS = ["standard", "standard32", "standardjtag", "ls180"]
+CPU_VARIANTS = ["standard", "standard32", "standardjtag",
+ "standardjtagtestgpio", "ls180",
+ "standardjtagnoirq"]
def make_wb_bus(prefix, obj, simple=False):
return res
def make_pad(res, dirn, name, suffix, cpup, iop):
+ print ("make pad", dirn, name, suffix, cpup, iop)
cpud, iod = ('i', 'o') if dirn else ('o', 'i')
res['%s_%s__core__%s' % (cpud, name, suffix)] = cpup
res['%s_%s__pad__%s' % (iod, name, suffix)] = iop
elif iotype == IOType.InTriOut:
if fn == 'gpio': # sigh decode GPIO special-case
idx = int(pin[1:])
+ oe_idx = idx
+ elif fn == 'sdr': # sigh
+ idx = int(pin.split('_')[-1])
+ oe_idx = 0
else:
idx = 0
+ oe_idx = 0
+ print ("gpio tri", fn, pin, iotype, pin_name, scan_idx, idx)
cpup, iop = get_field(cpu, "i")[idx], get_field(io, "i")[idx]
make_pad(res, False, name, "i", cpup, iop)
cpup, iop = get_field(cpu, "o")[idx], get_field(io, "o")[idx]
make_pad(res, True, name, "o", cpup, iop)
- cpup, iop = get_field(cpu, "oe")[idx], get_field(io, "oe")[idx]
+ cpup, iop = get_field(cpu, "oe")[oe_idx], get_field(io, "oe")[oe_idx]
make_pad(res, True, name, "oe", cpup, iop)
if iotype in (IOType.In, IOType.InTriOut):
self.platform = platform
self.variant = variant
self.reset = Signal()
+
irq_en = "noirq" not in variant
if irq_en:
jtag_en = ('jtag' in variant) or variant == 'ls180'
- if variant != "ls180":
+ if "testgpio" in variant:
self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
if jtag_en:
self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
o_busy_o = Signal(), # not connected
o_memerr_o = Signal(), # not connected
o_pc_o = Signal(64), # not connected
-
)
if irq_en:
self.clk_sel = Signal(3)
self.cpu_params['i_clk_sel_i'] = self.clk_sel
self.cpu_params['o_pll_48_o'] = self.pll_48_o
-
+
# add wishbone buses to cpu params
self.cpu_params.update(make_wb_bus("ibus", ibus))
self.cpu_params.update(make_wb_bus("dbus", dbus))
self.cpu_params.update(make_wb_slave("ics_wb", ics))
self.cpu_params.update(make_wb_slave("icp_wb", icp))
- if variant != "ls180":
+ if "testgpio" in variant:
self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
if jtag_en:
self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))