attempt to split into two separate GPIO banks due to a coriolis2 compile error

[soc.git] / src / soc / litex / florent / ls180soc.py

diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index 8566988ac1326f19c7d4ca67735bc55e5cc00e45..41979267086168976132457e1423f239a625d4a6 100755 (executable)
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -99,7 +99,7 @@ class I2CMaster(Module, AutoCSR):
 
 
 class GPIOTristateASIC(Module, AutoCSR):
-    def __init__(self, pads):
+    def __init__(self, pads, prange=None):
         nbits     = len(pads.oe) # hack
         self._oe  = CSRStorage(nbits, description="GPIO Tristate(s) Control.")
         self._in  = CSRStatus(nbits,  description="GPIO Input(s) Status.")
@@ -116,7 +116,9 @@ class GPIOTristateASIC(Module, AutoCSR):
 
         self.comb += _pads.oe.eq(self._oe.storage)
         self.comb += _pads.o.eq(self._out.storage)
-        for i in range(nbits):
+        if prange is None:
+            prange = range(nbits)
+        for i in prange:
             self.specials += MultiReg(_pads.i[i], self._in.status[i])
 
 # SDCard PHY IO -------------------------------------------------------
@@ -339,7 +341,8 @@ class LibreSoCSim(SoCCore):
             sdram_module          = sdram_module,
             sdram_data_width      = sdram_data_width,
             integrated_rom_size      = 0, # if ram_fname else 0x10000,
-            integrated_sram_size     = 0x1000,
+            #integrated_sram_size     = 0x1000, - problem with yosys ABC
+            integrated_sram_size     = 0x200,
             #integrated_main_ram_init  = ram_init,
             integrated_main_ram_size = 0x00000000 if with_sdram \
                                         else 0x10000000 , # 256MB
@@ -347,9 +350,9 @@ class LibreSoCSim(SoCCore):
         self.platform.name = "ls180"
 
         # add 3 more 4k integrated SRAMs
-        self.add_ram("sram1", self.mem_map["sram1"], 0x1000)
-        self.add_ram("sram2", self.mem_map["sram2"], 0x1000)
-        self.add_ram("sram3", self.mem_map["sram3"], 0x1000)
+        self.add_ram("sram1", self.mem_map["sram1"], 0x200)
+        self.add_ram("sram2", self.mem_map["sram2"], 0x200)
+        self.add_ram("sram3", self.mem_map["sram3"], 0x200)
 
         # SDR SDRAM ----------------------------------------------
         if False: # not self.integrated_main_ram_size:
@@ -440,9 +443,12 @@ class LibreSoCSim(SoCCore):
 
         # GPIOs (bi-directional)
         gpio_core_pads = self.cpu.cpupads['gpio']
-        self.submodules.gpio = GPIOTristateASIC(gpio_core_pads)
+        self.submodules.gpio = GPIOTristateASIC(gpio_core_pads, range(8))
         self.add_csr("gpio")
 
+        self.submodules.gpio = GPIOTristateASIC(gpio_core_pads, range(8,16))
+        self.add_csr("gpio1")
+
         # SPI Master
         print ("cpupadkeys", self.cpu.cpupads.keys())
         self.submodules.spimaster = SPIMaster(