attempt to split into two separate GPIO banks due to a coriolis2 compile error

[soc.git] / src / soc / litex / florent / ls180soc.py

diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index 93ed3890eb03c8fd7d326cb4d1400d67f090fc40..41979267086168976132457e1423f239a625d4a6 100755 (executable)
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -99,7 +99,7 @@ class I2CMaster(Module, AutoCSR):
 
 
 class GPIOTristateASIC(Module, AutoCSR):
-    def __init__(self, pads):
+    def __init__(self, pads, prange=None):
         nbits     = len(pads.oe) # hack
         self._oe  = CSRStorage(nbits, description="GPIO Tristate(s) Control.")
         self._in  = CSRStatus(nbits,  description="GPIO Input(s) Status.")
@@ -116,7 +116,9 @@ class GPIOTristateASIC(Module, AutoCSR):
 
         self.comb += _pads.oe.eq(self._oe.storage)
         self.comb += _pads.o.eq(self._out.storage)
-        for i in range(nbits):
+        if prange is None:
+            prange = range(nbits)
+        for i in prange:
             self.specials += MultiReg(_pads.i[i], self._in.status[i])
 
 # SDCard PHY IO -------------------------------------------------------
@@ -319,13 +321,16 @@ class LibreSoCSim(SoCCore):
 
         self.mem_map["main_ram"] = 0x90000000
         self.mem_map["sram"] = 0x00000000
+        self.mem_map["sram1"] = 0x00001000
+        self.mem_map["sram2"] = 0x00002000
+        self.mem_map["sram3"] = 0x00003000
 
         # SoCCore -------------------------------------------------------------
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
             cpu_type                 = "microwatt",
             cpu_cls                  = LibreSoC   if cpu == "libresoc" \
                                        else Microwatt,
-            #bus_data_width           = 64,
+            bus_data_width           = 64,
             csr_address_width        = 14, # limit to 0x8000
             cpu_variant              = variant,
             csr_data_width            = 8,
@@ -336,6 +341,7 @@ class LibreSoCSim(SoCCore):
             sdram_module          = sdram_module,
             sdram_data_width      = sdram_data_width,
             integrated_rom_size      = 0, # if ram_fname else 0x10000,
+            #integrated_sram_size     = 0x1000, - problem with yosys ABC
             integrated_sram_size     = 0x200,
             #integrated_main_ram_init  = ram_init,
             integrated_main_ram_size = 0x00000000 if with_sdram \
@@ -343,6 +349,11 @@ class LibreSoCSim(SoCCore):
             )
         self.platform.name = "ls180"
 
+        # add 3 more 4k integrated SRAMs
+        self.add_ram("sram1", self.mem_map["sram1"], 0x200)
+        self.add_ram("sram2", self.mem_map["sram2"], 0x200)
+        self.add_ram("sram3", self.mem_map["sram3"], 0x200)
+
         # SDR SDRAM ----------------------------------------------
         if False: # not self.integrated_main_ram_size:
             self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
@@ -365,21 +376,15 @@ class LibreSoCSim(SoCCore):
 
         # PLL/Clock Select
         clksel_i = platform.request("sys_clksel_i")
-        pll48_o = platform.request("sys_pll_48_o")
+        pll18_o = platform.request("sys_pll_18_o")
+        pll_lck_o = platform.request("sys_pll_lck_o")
 
         self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
-        self.comb += pll48_o.eq(self.cpu.pll_48_o) # "test feed" from the PLL
+        self.comb += pll18_o.eq(self.cpu.pll_18_o) # "test feed" from the PLL
+        self.comb += pll_lck_o.eq(self.cpu.pll_lck_o) # PLL lock flag
 
         #ram_init = []
 
-        if False:
-            # for niolib temporary hack
-            io_in = Signal()
-            io_out = Signal()
-
-            self.comb += io_in.eq(self.cpu.io_in)
-            self.comb += io_out.eq(self.cpu.io_out)
-
         # SDRAM ----------------------------------------------------
         if with_sdram:
             sdram_clk_freq   = int(100e6) # FIXME: use 100MHz timings
@@ -438,9 +443,12 @@ class LibreSoCSim(SoCCore):
 
         # GPIOs (bi-directional)
         gpio_core_pads = self.cpu.cpupads['gpio']
-        self.submodules.gpio = GPIOTristateASIC(gpio_core_pads)
+        self.submodules.gpio = GPIOTristateASIC(gpio_core_pads, range(8))
         self.add_csr("gpio")
 
+        self.submodules.gpio = GPIOTristateASIC(gpio_core_pads, range(8,16))
+        self.add_csr("gpio1")
+
         # SPI Master
         print ("cpupadkeys", self.cpu.cpupads.keys())
         self.submodules.spimaster = SPIMaster(