class GPIOTristateASIC(Module, AutoCSR):
- def __init__(self, pads):
+ def __init__(self, pads, prange=None):
nbits = len(pads.oe) # hack
self._oe = CSRStorage(nbits, description="GPIO Tristate(s) Control.")
self._in = CSRStatus(nbits, description="GPIO Input(s) Status.")
self.comb += _pads.oe.eq(self._oe.storage)
self.comb += _pads.o.eq(self._out.storage)
- for i in range(nbits):
+ if prange is None:
+ prange = range(nbits)
+ for i in prange:
self.specials += MultiReg(_pads.i[i], self._in.status[i])
# SDCard PHY IO -------------------------------------------------------
self.platform.name = "ls180"
# add 3 more 4k integrated SRAMs
- self.add_ram("sram1", self.mem_map["sram1"], 0x1000)
- self.add_ram("sram2", self.mem_map["sram2"], 0x1000)
- self.add_ram("sram3", self.mem_map["sram3"], 0x1000)
+ self.add_ram("sram1", self.mem_map["sram1"], 0x200)
+ self.add_ram("sram2", self.mem_map["sram2"], 0x200)
+ self.add_ram("sram3", self.mem_map["sram3"], 0x200)
# SDR SDRAM ----------------------------------------------
if False: # not self.integrated_main_ram_size:
# GPIOs (bi-directional)
gpio_core_pads = self.cpu.cpupads['gpio']
- self.submodules.gpio = GPIOTristateASIC(gpio_core_pads)
+ self.submodules.gpio = GPIOTristateASIC(gpio_core_pads, range(8))
self.add_csr("gpio")
+ self.submodules.gpio = GPIOTristateASIC(gpio_core_pads, range(8,16))
+ self.add_csr("gpio1")
+
# SPI Master
print ("cpupadkeys", self.cpu.cpupads.keys())
self.submodules.spimaster = SPIMaster(