record commands for building ECP5

[soc.git] / src / soc / litex / florent / ls180soc.py

diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index 29d89122f12675a76e2c57609fc4cd45942cd749..4279effcffe2fbf15f877e9b2a1b76beab248dac 100755 (executable)
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -385,7 +385,8 @@ class LibreSoCSim(SoCCore):
                             clk_freq   = sdram_clk_freq)
             #sdrphy_cls = HalfRateGENSDRPHY
             sdrphy_cls = GENSDRPHY
-            self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
+            sdram_pads = self.cpu.cpupads['sdr']
+            self.submodules.sdrphy = sdrphy_cls(sdram_pads)
             #self.submodules.sdrphy = sdrphy_cls(sdram_module,
             #                                       phy_settings,
             #                                       init=ram_init
@@ -409,7 +410,7 @@ class LibreSoCSim(SoCCore):
 
             # SDRAM clock
             sys_clk = ClockSignal()
-            sdr_clk = platform.request("sdram_clock")
+            sdr_clk = self.cpu.cpupads['sdram_clock']
             #self.specials += DDROutput(1, 0, , sdram_clk)
             self.specials += SDROutput(clk=sys_clk, i=sys_clk, o=sdr_clk)
 
@@ -520,6 +521,8 @@ class LibreSoCSim(SoCCore):
         if not debug:
             return
 
+        jtag_en = ('jtag' in variant) or variant == 'ls180'
+
         # setup running of DMI FSM
         dmi_addr = Signal(4)
         dmi_din = Signal(64)