self.submodules.crg = CRG(platform.request("sys_clk"),
platform.request("sys_rst"))
+ # PLL/Clock Select
+ clksel_i = platform.request("sys_clksel_i")
+ pll48_o = platform.request("sys_pll_48_o")
+
+ self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
+ self.comb += pll48_o.eq(self.cpu.pll_48_o) # "test feed" from the PLL
+
#ram_init = []
# SDRAM ----------------------------------------------------
self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
tx_fifo_depth = 16,
rx_fifo_depth = 16))
- # "real" pads connect to C4M JTAG iopad
- uart_pads = platform.request(uart_name) # "real" (actual) pin
- uart_io_pads = self.cpu.iopads['uart'] # C4M JTAG pads
- self.comb += uart_pads.tx.eq(uart_io_pads.tx)
- self.comb += uart_io_pads.rx.eq(uart_pads.rx)
self.csr.add("uart_phy", use_loc_if_exists=True)
self.csr.add("uart", use_loc_if_exists=True)
self.submodules.gpio = GPIOTristateASIC(gpio_core_pads)
self.add_csr("gpio")
- gpio_pads = platform.request("gpio") # "real" (actual) pins
- gpio_io_pads = self.cpu.iopads['gpio'] # C4M JTAG pads
- self.comb += gpio_io_pads.i.eq(gpio_pads.i)
- self.comb += gpio_pads.o.eq(gpio_io_pads.o)
- self.comb += gpio_pads.oe.eq(gpio_io_pads.oe)
-
# SPI Master
self.submodules.spi_master = SPIMaster(
pads = platform.request("spi_master"),