nope. put it back and connect to platform pads in LS180Platform

[soc.git] / src / soc / litex / florent / ls180soc.py

diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index fd6c84b95f20b05bcdf1876c440ae84652d2afd0..50d2a95f9ff1bc781c112eb3ea0e78885c813693 100755 (executable)
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -47,7 +47,7 @@ SoCCSRHandler.supported_address_width.append(12)
 # GPIO Tristate -------------------------------------------------------
 # doesn't work properly.
 #from litex.soc.cores.gpio import GPIOTristate
-from litex.soc.interconnect.csr import CSRStorage, CSRStatus
+from litex.soc.interconnect.csr import CSRStorage, CSRStatus, CSRField
 from migen.genlib.cdc import MultiReg
 
 # Imports
@@ -363,6 +363,13 @@ class LibreSoCSim(SoCCore):
         self.submodules.crg = CRG(platform.request("sys_clk"),
                                   platform.request("sys_rst"))
 
+        # PLL/Clock Select
+        clksel_i = platform.request("sys_clksel_i")
+        pll48_o = platform.request("sys_pll_48_o")
+
+        self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
+        self.comb += pll48_o.eq(self.cpu.pll_48_o) # "test feed" from the PLL
+
         #ram_init = []
 
         # SDRAM ----------------------------------------------------
@@ -415,11 +422,6 @@ class LibreSoCSim(SoCCore):
         self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
                 tx_fifo_depth = 16,
                 rx_fifo_depth = 16))
-        # "real" pads connect to C4M JTAG iopad
-        uart_pads     = platform.request(uart_name) # "real" (actual) pin
-        uart_io_pads = self.cpu.iopads['uart'] # C4M JTAG pads
-        self.comb += uart_pads.tx.eq(uart_io_pads.tx)
-        self.comb += uart_io_pads.rx.eq(uart_pads.rx)
 
         self.csr.add("uart_phy", use_loc_if_exists=True)
         self.csr.add("uart", use_loc_if_exists=True)
@@ -430,12 +432,6 @@ class LibreSoCSim(SoCCore):
         self.submodules.gpio = GPIOTristateASIC(gpio_core_pads)
         self.add_csr("gpio")
 
-        gpio_pads = platform.request("gpio") # "real" (actual) pins
-        gpio_io_pads = self.cpu.iopads['gpio'] # C4M JTAG pads
-        self.comb += gpio_io_pads.i.eq(gpio_pads.i)
-        self.comb += gpio_pads.o.eq(gpio_io_pads.o)
-        self.comb += gpio_pads.oe.eq(gpio_io_pads.oe)
-
         # SPI Master
         self.submodules.spi_master = SPIMaster(
             pads         = platform.request("spi_master"),
@@ -471,10 +467,9 @@ class LibreSoCSim(SoCCore):
             setattr(self.submodules, name, PWM(platform.request("pwm", i)))
             self.add_csr(name)
 
-        if False: # TODO: convert to _i _o _oe
-            # I2C Master
-            self.submodules.i2c = I2CMaster(platform.request("i2c"))
-            self.add_csr("i2c")
+        # I2C Master
+        self.submodules.i2c = I2CMaster(platform.request("i2c"))
+        self.add_csr("i2c")
 
         # SDCard -----------------------------------------------------