sigh sorting out litex pin-connections to sdram

[soc.git] / src / soc / litex / florent / ls180soc.py

diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index 4279effcffe2fbf15f877e9b2a1b76beab248dac..93ed3890eb03c8fd7d326cb4d1400d67f090fc40 100755 (executable)
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -372,6 +372,14 @@ class LibreSoCSim(SoCCore):
 
         #ram_init = []
 
+        if False:
+            # for niolib temporary hack
+            io_in = Signal()
+            io_out = Signal()
+
+            self.comb += io_in.eq(self.cpu.io_in)
+            self.comb += io_out.eq(self.cpu.io_out)
+
         # SDRAM ----------------------------------------------------
         if with_sdram:
             sdram_clk_freq   = int(100e6) # FIXME: use 100MHz timings