self.mem_map["main_ram"] = 0x90000000
self.mem_map["sram"] = 0x00000000
+ self.mem_map["sram1"] = 0x00001000
+ self.mem_map["sram2"] = 0x00002000
+ self.mem_map["sram3"] = 0x00003000
# SoCCore -------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
cpu_type = "microwatt",
cpu_cls = LibreSoC if cpu == "libresoc" \
else Microwatt,
- #bus_data_width = 64,
+ bus_data_width = 64,
csr_address_width = 14, # limit to 0x8000
cpu_variant = variant,
csr_data_width = 8,
sdram_module = sdram_module,
sdram_data_width = sdram_data_width,
integrated_rom_size = 0, # if ram_fname else 0x10000,
+ #integrated_sram_size = 0x1000, - problem with yosys ABC
integrated_sram_size = 0x200,
#integrated_main_ram_init = ram_init,
integrated_main_ram_size = 0x00000000 if with_sdram \
)
self.platform.name = "ls180"
+ # add 3 more 4k integrated SRAMs
+ self.add_ram("sram1", self.mem_map["sram1"], 0x1000)
+ self.add_ram("sram2", self.mem_map["sram2"], 0x1000)
+ self.add_ram("sram3", self.mem_map["sram3"], 0x1000)
+
# SDR SDRAM ----------------------------------------------
if False: # not self.integrated_main_ram_size:
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
# PLL/Clock Select
clksel_i = platform.request("sys_clksel_i")
- pll48_o = platform.request("sys_pll_48_o")
+ pll18_o = platform.request("sys_pll_18_o")
+ pll_lck_o = platform.request("sys_pll_lck_o")
self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
- self.comb += pll48_o.eq(self.cpu.pll_48_o) # "test feed" from the PLL
+ self.comb += pll18_o.eq(self.cpu.pll_18_o) # "test feed" from the PLL
+ self.comb += pll_lck_o.eq(self.cpu.pll_lck_o) # PLL lock flag
#ram_init = []
- if False:
- # for niolib temporary hack
- io_in = Signal()
- io_out = Signal()
-
- self.comb += io_in.eq(self.cpu.io_in)
- self.comb += io_out.eq(self.cpu.io_out)
-
# SDRAM ----------------------------------------------------
if with_sdram:
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings