argh issue with yosys ABC

[soc.git] / src / soc / litex / florent / ls180soc.py

diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index 9da9d180a23c45448ddd1d1628549e1eb88791a6..f8c71ebbbaf55bf685ed18639a1cb8bfcf66f280 100755 (executable)
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -319,13 +319,16 @@ class LibreSoCSim(SoCCore):
 
         self.mem_map["main_ram"] = 0x90000000
         self.mem_map["sram"] = 0x00000000
+        self.mem_map["sram1"] = 0x00001000
+        self.mem_map["sram2"] = 0x00002000
+        self.mem_map["sram3"] = 0x00003000
 
         # SoCCore -------------------------------------------------------------
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
             cpu_type                 = "microwatt",
             cpu_cls                  = LibreSoC   if cpu == "libresoc" \
                                        else Microwatt,
-            #bus_data_width           = 64,
+            bus_data_width           = 64,
             csr_address_width        = 14, # limit to 0x8000
             cpu_variant              = variant,
             csr_data_width            = 8,
@@ -336,6 +339,7 @@ class LibreSoCSim(SoCCore):
             sdram_module          = sdram_module,
             sdram_data_width      = sdram_data_width,
             integrated_rom_size      = 0, # if ram_fname else 0x10000,
+            #integrated_sram_size     = 0x1000, - problem with yosys ABC
             integrated_sram_size     = 0x200,
             #integrated_main_ram_init  = ram_init,
             integrated_main_ram_size = 0x00000000 if with_sdram \
@@ -343,6 +347,11 @@ class LibreSoCSim(SoCCore):
             )
         self.platform.name = "ls180"
 
+        # add 3 more 4k integrated SRAMs
+        self.add_ram("sram1", self.mem_map["sram1"], 0x1000)
+        self.add_ram("sram2", self.mem_map["sram2"], 0x1000)
+        self.add_ram("sram3", self.mem_map["sram3"], 0x1000)
+
         # SDR SDRAM ----------------------------------------------
         if False: # not self.integrated_main_ram_size:
             self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
@@ -365,10 +374,12 @@ class LibreSoCSim(SoCCore):
 
         # PLL/Clock Select
         clksel_i = platform.request("sys_clksel_i")
-        pll48_o = platform.request("sys_pll_48_o")
+        pll18_o = platform.request("sys_pll_18_o")
+        pll_lck_o = platform.request("sys_pll_lck_o")
 
         self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
-        self.comb += pll48_o.eq(self.cpu.pll_48_o) # "test feed" from the PLL
+        self.comb += pll18_o.eq(self.cpu.pll_18_o) # "test feed" from the PLL
+        self.comb += pll_lck_o.eq(self.cpu.pll_lck_o) # PLL lock flag
 
         #ram_init = []
 
@@ -521,6 +532,8 @@ class LibreSoCSim(SoCCore):
         if not debug:
             return
 
+        jtag_en = ('jtag' in variant) or variant == 'ls180'
+
         # setup running of DMI FSM
         dmi_addr = Signal(4)
         dmi_din = Signal(64)