use copy of FHDLTestCase

[soc.git] / src / soc / regfile / formal / proof_regfile_array.py

diff --git a/src/soc/regfile/formal/proof_regfile_array.py b/src/soc/regfile/formal/proof_regfile_array.py
index b35c51eb516ae134b36c9db3e13ac90be08a3559..fc7c293c9179be18021c928b0c7dc74c59c68e86 100644 (file)
--- a/src/soc/regfile/formal/proof_regfile_array.py
+++ b/src/soc/regfile/formal/proof_regfile_array.py
@@ -4,7 +4,7 @@ from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl,
                     signed, ResetSignal, Array)
 from nmigen.asserts import (Assert, AnySeq, Assume, Cover, Initial,
                             Rose, Fell, Stable, Past)
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 import unittest