add support for DMI debug read of FAST Regfile SPRs

[soc.git] / src / soc / regfile / regfiles.py

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 754b6902e0aa04f31b82de168fa1a40a035372d3..f3531e092a335fb7ef2baa0e306af5fb1b72370d 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -158,6 +158,7 @@ class FastRegs(RegFileMem, FastRegsEnum): #RegFileArray):
                        }
         r_port_spec = {'fast1': "src1",
                        'issue': "issue", # reading DEC/TB
+                        'dmi': "dmi" # needed for Debug (DMI)
                         }
         if not self.regreduce_en:
             r_port_spec['fast2'] = "src2"