move DEC and TB into StateRegs, to make room in FastRegs

[soc.git] / src / soc / simple / core.py

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 8df7e17ad1d1525233404694cb7602e708227b4d..507302f451a18e0a4f5252d4c8f088e58e05a420 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -164,7 +164,9 @@ class NonProductionCore(ControlBase):
             self.msr_at_reset = pspec.msr_reset
         state_resets = [0x0,               # PC at reset
                         self.msr_at_reset, # MSR at reset
-                        0x0]               # SVSTATE at reset
+                        0x0,               # SVSTATE at reset
+                        0x0,               # DEC at reset
+                        0x0]               # TB at reset
 
         # register files (yes plural)
         self.regs = RegFiles(pspec, make_hazard_vecs=self.make_hazard_vecs,