make core_rst a member of TestIssuerInternal

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index c604354ad82a0c26bc09f026a0a04c0641d19c99..8e98202ca4506cf479df6b70f44f3a8a94206db3 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -216,6 +216,7 @@ class TestIssuerInternal(Elaboratable):
 
         # main instruction core.  suitable for prototyping / demo only
         self.core = core = NonProductionCore(pspec)
+        self.core_rst = ResetSignal("coresync")
 
         # instruction decoder.  goes into Trap Record
         pdecode = create_pdecode()
@@ -966,7 +967,8 @@ class TestIssuerInternal(Elaboratable):
         core = self.core
 
         # set up peripherals and core
-        core_rst = self.setup_peripherals(m)
+        core_rst = self.core_rst
+        self.setup_peripherals(m)
 
         # reset current state if core reset requested
         with m.If(core_rst):