adjust PLL connections looking for coriolis2 issue

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index d8a3d486e358608c3d5bfaf77e0ba841083e642c..c604354ad82a0c26bc09f026a0a04c0641d19c99 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -1276,7 +1276,7 @@ class TestIssuer(Elaboratable):
         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
         intclk = ClockSignal("coresync")
         if self.pll_en:
-            comb += intclk.eq(pll.clk_pll_o)
+            comb += intclk.eq(pllclk)
         else:
             comb += intclk.eq(ClockSignal())