update SVSTATE to 64 bit length (fortunately very easy)

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 465ade0e4c9abc2bd5326fa111bcfaebb298a767..feef6b62a24b6e27a7f5d601c3096a9d494378bd 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -242,7 +242,7 @@ class TestIssuerInternal(Elaboratable):
         # instruction go/monitor
         self.pc_o = Signal(64, reset_less=True)
         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
-        self.svstate_i = Data(32, "svstate_i") # ditto
+        self.svstate_i = Data(64, "svstate_i") # ditto
         self.core_bigendian_i = Signal() # TODO: set based on MSR.LE
         self.busy_o = Signal(reset_less=True)
         self.memerr_o = Signal(reset_less=True)