add query about cross-domain on the JTAG enable of WB

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 64350c96ab1bc7a93ee089a4c68dd28afcc457b3..27afb68ed4546c2751f87f35db7373f845c7464b 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -50,6 +50,22 @@ class TestIssuerInternal(Elaboratable):
     """
     def __init__(self, pspec):
 
+        # JTAG interface.  add this right at the start because if it's
+        # added it *modifies* the pspec, by adding enable/disable signals
+        # for parts of the rest of the core
+        self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
+        if self.jtag_en:
+            subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
+                      'pwm', 'sd0', 'sdr'}
+            self.jtag = JTAG(get_pinspecs(subset=subset))
+            # add signals to pspec to enable/disable icache and dcache
+            # (or data and intstruction wishbone if icache/dcache not included)
+            # https://bugs.libre-soc.org/show_bug.cgi?id=520
+            # TODO: do we actually care if these are not domain-synchronised?
+            # honestly probably not.
+            pspec.wb_icache_en = self.jtag.wb_icache_en
+            pspec.wb_dcache_en = self.jtag.wb_dcache_en
+
         # add interrupt controller?
         self.xics = hasattr(pspec, "xics") and pspec.xics == True
         if self.xics:
@@ -81,13 +97,6 @@ class TestIssuerInternal(Elaboratable):
         # DMI interface
         self.dbg = CoreDebug()
 
-        # JTAG interface
-        self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
-        if self.jtag_en:
-            subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
-                      'pwm', 'sd0', 'sdr'}
-            self.jtag = JTAG(get_pinspecs(subset=subset))
-
         # instruction go/monitor
         self.pc_o = Signal(64, reset_less=True)
         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
@@ -117,7 +126,7 @@ class TestIssuerInternal(Elaboratable):
         m = Module()
         comb, sync = m.d.comb, m.d.sync
 
-        m.submodules.core = core = self.core
+        m.submodules.core = core = DomainRenamer("coresync")(self.core)
         m.submodules.imem = imem = self.imem
         m.submodules.dbg = dbg = self.dbg
         if self.jtag_en:
@@ -156,7 +165,8 @@ class TestIssuerInternal(Elaboratable):
         # clock delay power-on reset
         cd_por  = ClockDomain(reset_less=True)
         cd_sync = ClockDomain()
-        m.domains += cd_por, cd_sync
+        core_sync = ClockDomain("coresync")
+        m.domains += cd_por, cd_sync, core_sync
 
         ti_rst = Signal(reset_less=True)
         delay = Signal(range(4), reset=3)
@@ -452,31 +462,31 @@ class TestIssuer(Elaboratable):
         self.clksel = ClockSelect()
 
         # PLL direct clock or not
-        self.pll_en = hasattr(pspec, "use_pll") and pspec.pll_en
+        self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
 
-        if self.pll_en:
-            # TestIssuer runs at internal clock rate
-            m.submodules.ti = ti = DomainRenamer("intclk")(self.ti)
-        else:
-            # TestIssuer runs at direct clock
-            m.submodules.ti = ti = self.ti
+        # TestIssuer runs at direct clock
+        m.submodules.ti = ti = self.ti
+        cd_int = ClockDomain("coresync")
+
         # ClockSelect runs at PLL output internal clock rate
         m.submodules.clksel = clksel = DomainRenamer("pllclk")(self.clksel)
         m.submodules.pll = pll = self.pll
 
         # add 2 clock domains established above...
-        cd_int = ClockDomain("intclk")
         cd_pll = ClockDomain("pllclk")
         m.domains += cd_pll
 
         # internal clock is set to selector clock-out.  has the side-effect of
         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
-        intclk = ClockSignal("intclk")
-        comb += intclk.eq(clksel.core_clk_o)
+        intclk = ClockSignal("coresync")
+        if self.pll_en:
+            comb += intclk.eq(clksel.core_clk_o)
+        else:
+            comb += intclk.eq(ClockSignal())
 
         # PLL clock established.  has the side-effect of running clklsel
         # at the PLL's speed (see DomainRenamer("pllclk") above)
@@ -488,9 +498,9 @@ class TestIssuer(Elaboratable):
         comb += pll.clk_24_i.eq(clksel.clk_24_i)
 
         # now wire up ResetSignals.  don't mind them all being in this domain
-        int_rst = ResetSignal("intclk")
+        #int_rst = ResetSignal("coresync")
         pll_rst = ResetSignal("pllclk")
-        comb += int_rst.eq(ResetSignal())
+        #comb += int_rst.eq(ResetSignal())
         comb += pll_rst.eq(ResetSignal())
 
         return m