rename and add pll lock signal to ls180

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index c231702f49f10fbac273da58e8da5f6e97ce50d2..5a62fdcd8a418cd72328932cd65c028e4ea456c6 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -513,7 +513,7 @@ class TestIssuer(Elaboratable):
         if self.pll_en:
             ports.append(self.pll.clk_sel_i)
             ports.append(self.pll.pll_18_o)
-            ports.append(self.pll.clk_lck_o)
+            ports.append(self.pll.pll_lck_o)
         return ports