from soc.decoder.power_decoder import create_pdecode
from soc.decoder.power_decoder2 import PowerDecode2
+from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
from soc.decoder.decode2execute1 import Data
from soc.experiment.testmem import TestMemory # test only for instructions
-from soc.regfile.regfiles import StateRegs
+from soc.regfile.regfiles import StateRegs, FastRegs
from soc.simple.core import NonProductionCore
from soc.config.test.test_loadstore import TestMemPspec
from soc.config.ifetch import ConfigFetchUnit
from soc.decoder.power_enums import MicrOp
from soc.debug.dmi import CoreDebug, DMIInterface
+from soc.debug.jtag import JTAG
+from soc.config.pinouts import get_pinspecs
from soc.config.state import CoreState
from soc.interrupts.xics import XICS_ICP, XICS_ICS
from soc.bus.simple_gpio import SimpleGPIO
+from soc.clock.select import ClockSelect, DummyPLL
+
from nmutil.util import rising_edge
-class TestIssuer(Elaboratable):
+class TestIssuerInternal(Elaboratable):
"""TestIssuer - reads instructions from TestMemory and issues them
efficiency and speed is not the main goal here: functional correctness is.
self.simple_gpio = SimpleGPIO()
self.gpio_o = self.simple_gpio.gpio_o
- # main instruction core
+ # main instruction core25
self.core = core = NonProductionCore(pspec)
- # instruction decoder
+ # instruction decoder. goes into Trap Record
pdecode = create_pdecode()
- self.pdecode2 = PowerDecode2(pdecode) # decoder
+ self.cur_state = CoreState("cur") # current state (MSR/PC/EINT)
+ self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
+ opkls=IssuerDecode2ToOperand)
# Test Instruction memory
self.imem = ConfigFetchUnit(pspec).fu
# DMI interface
self.dbg = CoreDebug()
+ # JTAG interface
+ self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
+ if self.jtag_en:
+ subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
+ 'pwm', 'sd0', 'sdr'}
+ self.jtag = JTAG(get_pinspecs(subset=subset))
+
# instruction go/monitor
self.pc_o = Signal(64, reset_less=True)
self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
self.busy_o = Signal(reset_less=True)
self.memerr_o = Signal(reset_less=True)
- # FAST regfile read /write ports for PC and MSR
+ # FAST regfile read /write ports for PC, MSR, DEC/TB
staterf = self.core.regs.rf['state']
self.state_r_pc = staterf.r_ports['cia'] # PC rd
self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
m.submodules.core = core = DomainRenamer("coresync")(self.core)
m.submodules.imem = imem = self.imem
m.submodules.dbg = dbg = self.dbg
+ if self.jtag_en:
+ m.submodules.jtag = jtag = self.jtag
+ # TODO: UART2GDB mux, here, from external pin
+ # see https://bugs.libre-soc.org/show_bug.cgi?id=499
+ sync += dbg.dmi.connect_to(jtag.dmi)
- # current state (MSR/PC at the moment
- cur_state = CoreState("cur")
+ cur_state = self.cur_state
# XICS interrupt handler
if self.xics:
core_sync = ClockDomain("coresync")
m.domains += cd_por, cd_sync, core_sync
+ ti_rst = Signal(reset_less=True)
delay = Signal(range(4), reset=3)
with m.If(delay != 0):
m.d.por += delay.eq(delay - 1)
comb += cd_por.clk.eq(ClockSignal())
comb += core_sync.clk.eq(ClockSignal())
+
# power-on reset delay
- comb += core.core_reset_i.eq(delay != 0 | dbg.core_rst_o)
+ core_rst = ResetSignal("coresync")
+ comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
+ comb += core_rst.eq(ti_rst)
# busy/halted signals from core
comb += self.busy_o.eq(core.busy_o)
dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
insn_type = core.e.do.insn_type
- dec_state = pdecode2.state
# actually use a nmigen FSM for the first time (w00t)
# this FSM is perhaps unusual in that it detects conditions
with m.State("IDLE"):
sync += pc_changed.eq(0)
sync += core.e.eq(0)
- with m.If(~dbg.core_stop_o & ~core.core_reset_i):
+ sync += core.raw_insn_i.eq(0)
+ sync += core.bigendian_i.eq(0)
+ with m.If(~dbg.core_stop_o & ~core_rst):
# instruction allowed to go: start by reading the PC
# capture the PC and also drop it into Insn Memory
# we have joined a pair of combinatorial memory
comb += self.imem.f_valid_i.eq(1)
sync += cur_state.pc.eq(pc)
- # initiate read of MSR
+ # initiate read of MSR. arrives one clock later
comb += self.state_r_msr.ren.eq(1<<StateRegs.MSR)
sync += msr_read.eq(0)
# dummy pause to find out why simulation is not keeping up
with m.State("INSN_READ"):
- # one cycle later, msr read arrives
+ # one cycle later, msr read arrives. valid only once.
with m.If(~msr_read):
- sync += msr_read.eq(1)
+ sync += msr_read.eq(1) # yeah don't read it again
sync += cur_state.msr.eq(self.state_r_msr.data_o)
with m.If(self.imem.f_busy_o): # zzz...
# busy: stay in wait-read
else:
insn = f_instr_o.word_select(cur_state.pc[2], 32)
comb += dec_opcode_i.eq(insn) # actual opcode
- comb += dec_state.eq(cur_state)
sync += core.e.eq(pdecode2.e)
+ sync += core.state.eq(cur_state)
+ sync += core.raw_insn_i.eq(dec_opcode_i)
+ sync += core.bigendian_i.eq(self.core_bigendian_i)
sync += ilatch.eq(insn) # latch current insn
# also drop PC and MSR into decode "state"
m.next = "INSN_START" # move to "start"
comb += core_ivalid_i.eq(1) # instruction is valid
comb += core_issue_i.eq(1) # and issued
-
m.next = "INSN_ACTIVE" # move to "wait completion"
# instruction started: must wait till it finishes
comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
comb += self.state_w_pc.data_i.eq(nia)
sync += core.e.eq(0)
+ sync += core.raw_insn_i.eq(0)
+ sync += core.bigendian_i.eq(0)
m.next = "IDLE" # back to idle
# this bit doesn't have to be in the FSM: connect up to read
comb += d_xer.data.eq(self.xer_r.data_o)
comb += d_xer.ack.eq(1)
+ # DEC and TB inc/dec FSM
+ self.tb_dec_fsm(m, cur_state.dec)
+
+ return m
+
+ def tb_dec_fsm(self, m, spr_dec):
+ """tb_dec_fsm
+
+ this is a FSM for updating either dec or tb. it runs alternately
+ DEC, TB, DEC, TB. note that SPR pipeline could have written a new
+ value to DEC, however the regfile has "passthrough" on it so this
+ *should* be ok.
+
+ see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
+ """
+
+ comb, sync = m.d.comb, m.d.sync
+ fast_rf = self.core.regs.rf['fast']
+ fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
+ fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
+
+ with m.FSM() as fsm:
+
+ # initiates read of current DEC
+ with m.State("DEC_READ"):
+ comb += fast_r_dectb.addr.eq(FastRegs.DEC)
+ comb += fast_r_dectb.ren.eq(1)
+ m.next = "DEC_WRITE"
+
+ # waits for DEC read to arrive (1 cycle), updates with new value
+ with m.State("DEC_WRITE"):
+ new_dec = Signal(64)
+ # TODO: MSR.LPCR 32-bit decrement mode
+ comb += new_dec.eq(fast_r_dectb.data_o - 1)
+ comb += fast_w_dectb.addr.eq(FastRegs.DEC)
+ comb += fast_w_dectb.wen.eq(1)
+ comb += fast_w_dectb.data_i.eq(new_dec)
+ sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
+ m.next = "TB_READ"
+
+ # initiates read of current TB
+ with m.State("TB_READ"):
+ comb += fast_r_dectb.addr.eq(FastRegs.TB)
+ comb += fast_r_dectb.ren.eq(1)
+ m.next = "TB_WRITE"
+
+ # waits for read TB to arrive, initiates write of current TB
+ with m.State("TB_WRITE"):
+ new_tb = Signal(64)
+ comb += new_tb.eq(fast_r_dectb.data_o + 1)
+ comb += fast_w_dectb.addr.eq(FastRegs.TB)
+ comb += fast_w_dectb.wen.eq(1)
+ comb += fast_w_dectb.data_i.eq(new_tb)
+ m.next = "DEC_READ"
+
return m
def __iter__(self):
def external_ports(self):
ports = self.pc_i.ports()
ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
- ClockSignal(), ResetSignal(),
]
- ports += list(self.dbg.dmi.ports())
+
+ if self.jtag_en:
+ ports += list(self.jtag.external_ports())
+ else:
+ # don't add DMI if JTAG is enabled
+ ports += list(self.dbg.dmi.ports())
+
ports += list(self.imem.ibus.fields.values())
ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
return list(self)
+class TestIssuer(Elaboratable):
+ def __init__(self, pspec):
+ self.ti = TestIssuerInternal(pspec)
+ self.pll = DummyPLL()
+ self.clksel = ClockSelect()
+
+ def elaborate(self, platform):
+ m = Module()
+ comb = m.d.comb
+
+ # TestIssuer runs at internal clock rate
+ m.submodules.ti = ti = DomainRenamer("intclk")(self.ti)
+ # ClockSelect runs at PLL output internal clock rate
+ m.submodules.clksel = clksel = DomainRenamer("pllclk")(self.clksel)
+ m.submodules.pll = pll = self.pll
+
+ # add 2 clock domains established above...
+ cd_int = ClockDomain("intclk")
+ cd_pll = ClockDomain("pllclk")
+ # probably don't have to add cd_int because of DomainRenamer("coresync")
+ m.domains += cd_pll
+
+ # internal clock is set to selector clock-out. has the side-effect of
+ # running TestIssuer at this speed (see DomainRenamer("intclk") above)
+ comb += cd_int.clk.eq(clksel.core_clk_o)
+
+ # PLL clock established. has the side-effect of running clklsel
+ # at the PLL's speed (see DomainRenamer("pllclk") above)
+ comb += cd_pll.clk.eq(pll.clk_pll_o)
+
+ # wire up external 24mhz to PLL and clksel
+ comb += clksel.clk_24_i.eq(ClockSignal())
+ comb += pll.clk_24_i.eq(clksel.clk_24_i)
+
+ # now wire up ResetSignals. don't mind them all being in this domain
+ int_rst = ResetSignal("intclk")
+ pll_rst = ResetSignal("pllclk")
+ comb += int_rst.eq(ResetSignal())
+ comb += pll_rst.eq(ResetSignal())
+
+ return m
+
+ def ports(self):
+ return list(self.ti.ports()) + list(self.pll.ports()) + \
+ [ClockSignal(), ResetSignal()] + \
+ list(self.clksel.ports())
+
+ def external_ports(self):
+ ports = self.ti.external_ports()
+ ports.append(ClockSignal())
+ ports.append(ResetSignal())
+ ports.append(self.clksel.clk_sel_i)
+ ports.append(self.clksel.pll_48_o)
+ return ports
+
+
if __name__ == '__main__':
units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
'spr': 1,
projects / soc.git / blobdiff