comment out XICS/GPIO interrupt test, causes ECP5 litex build to fail

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 7fb102fb94eb4c39eebc6908d3265799e2d6323a..aafae394e101cb4d9ab9aff0080a0b6e896cf36e 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -140,8 +140,10 @@ class TestIssuerInternal(Elaboratable):
             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 
         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
-        if self.gpio and self.xics:
-            comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
+        # XXX causes litex ECP5 test to get wrong idea about input and output
+        # (but works with verilator sim *sigh*)
+        #if self.gpio and self.xics:
+        #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 
         # instruction decoder
         pdecode = create_pdecode()