from soc.config.state import CoreState
from soc.interrupts.xics import XICS_ICP, XICS_ICS
from soc.bus.simple_gpio import SimpleGPIO
-from soc.clock.select import ClockSelect, DummyPLL
+from soc.clock.select import ClockSelect
+from soc.clock.dummypll import DummyPLL
from nmutil.util import rising_edge
"""
def __init__(self, pspec):
+ # JTAG interface. add this right at the start because if it's
+ # added it *modifies* the pspec, by adding enable/disable signals
+ # for parts of the rest of the core
+ self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
+ if self.jtag_en:
+ subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
+ 'pwm', 'sd0', 'sdr'}
+ self.jtag = JTAG(get_pinspecs(subset=subset))
+ # add signals to pspec to enable/disable icache and dcache
+ # (or data and intstruction wishbone if icache/dcache not included)
+ # https://bugs.libre-soc.org/show_bug.cgi?id=520
+ # TODO: do we actually care if these are not domain-synchronised?
+ # honestly probably not.
+ pspec.wb_icache_en = self.jtag.wb_icache_en
+ pspec.wb_dcache_en = self.jtag.wb_dcache_en
+
# add interrupt controller?
self.xics = hasattr(pspec, "xics") and pspec.xics == True
if self.xics:
# DMI interface
self.dbg = CoreDebug()
- # JTAG interface
- self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
- if self.jtag_en:
- subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
- 'pwm', 'sd0', 'sdr'}
- self.jtag = JTAG(get_pinspecs(subset=subset))
-
# instruction go/monitor
self.pc_o = Signal(64, reset_less=True)
self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
m = Module()
comb, sync = m.d.comb, m.d.sync
- m.submodules.core = core = self.core
+ m.submodules.core = core = DomainRenamer("coresync")(self.core)
m.submodules.imem = imem = self.imem
m.submodules.dbg = dbg = self.dbg
if self.jtag_en:
# clock delay power-on reset
cd_por = ClockDomain(reset_less=True)
cd_sync = ClockDomain()
- m.domains += cd_por, cd_sync
+ core_sync = ClockDomain("coresync")
+ m.domains += cd_por, cd_sync, core_sync
ti_rst = Signal(reset_less=True)
delay = Signal(range(4), reset=3)
m.d.por += delay.eq(delay - 1)
comb += cd_por.clk.eq(ClockSignal())
- # power-on reset delay
+ # power-on reset delay
core_rst = ResetSignal("coresync")
comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
comb += core_rst.eq(ti_rst)
class TestIssuer(Elaboratable):
def __init__(self, pspec):
self.ti = TestIssuerInternal(pspec)
+
self.pll = DummyPLL()
- self.clksel = ClockSelect()
+
+ # PLL direct clock or not
+ self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
def elaborate(self, platform):
m = Module()
comb = m.d.comb
- # TestIssuer runs at internal clock rate
- m.submodules.ti = ti = DomainRenamer("intclk")(self.ti)
- # ClockSelect runs at PLL output internal clock rate
- m.submodules.clksel = clksel = DomainRenamer("pllclk")(self.clksel)
- m.submodules.pll = pll = self.pll
+ # TestIssuer runs at direct clock
+ m.submodules.ti = ti = self.ti
+ cd_int = ClockDomain("coresync")
- # add 2 clock domains established above...
- cd_int = ClockDomain("intclk")
- cd_pll = ClockDomain("pllclk")
- m.domains += cd_pll
+ if self.pll_en:
+ # ClockSelect runs at PLL output internal clock rate
+ m.submodules.pll = pll = self.pll
- # internal clock is set to selector clock-out. has the side-effect of
- # running TestIssuer at this speed (see DomainRenamer("intclk") above)
- intclk = ClockSignal("intclk")
- comb += intclk.eq(clksel.core_clk_o)
+ # add clock domains from PLL
+ cd_pll = ClockDomain("pllclk")
+ m.domains += cd_pll
+
+ # PLL clock established. has the side-effect of running clklsel
+ # at the PLL's speed (see DomainRenamer("pllclk") above)
+ pllclk = ClockSignal("pllclk")
+ comb += pllclk.eq(pll.clk_pll_o)
- # PLL clock established. has the side-effect of running clklsel
- # at the PLL's speed (see DomainRenamer("pllclk") above)
- pllclk = ClockSignal("pllclk")
- comb += pllclk.eq(pll.clk_pll_o)
+ # wire up external 24mhz to PLL
+ comb += pll.clk_24_i.eq(ClockSignal())
- # wire up external 24mhz to PLL and clksel
- comb += clksel.clk_24_i.eq(ClockSignal())
- comb += pll.clk_24_i.eq(clksel.clk_24_i)
+ # now wire up ResetSignals. don't mind them being in this domain
+ pll_rst = ResetSignal("pllclk")
+ comb += pll_rst.eq(ResetSignal())
- # now wire up ResetSignals. don't mind them all being in this domain
- int_rst = ResetSignal("intclk")
- pll_rst = ResetSignal("pllclk")
- comb += int_rst.eq(ResetSignal())
- comb += pll_rst.eq(ResetSignal())
+ # internal clock is set to selector clock-out. has the side-effect of
+ # running TestIssuer at this speed (see DomainRenamer("intclk") above)
+ intclk = ClockSignal("coresync")
+ if self.pll_en:
+ comb += intclk.eq(pll.clk_pll_o)
+ else:
+ comb += intclk.eq(ClockSignal())
return m
def ports(self):
return list(self.ti.ports()) + list(self.pll.ports()) + \
- [ClockSignal(), ResetSignal()] + \
- list(self.clksel.ports())
+ [ClockSignal(), ResetSignal()]
def external_ports(self):
ports = self.ti.external_ports()
ports.append(ClockSignal())
ports.append(ResetSignal())
- ports.append(self.clksel.clk_sel_i)
- ports.append(self.clksel.pll_48_o)
+ if self.pll_en:
+ ports.append(self.pll.clk_sel_i)
+ ports.append(self.pll.pll_18_o)
+ ports.append(self.pll.clk_lck_o)
return ports
projects / soc.git / blobdiff