from soc.decoder.power_decoder import create_pdecode
from soc.decoder.power_decoder2 import PowerDecode2
+from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
from soc.decoder.decode2execute1 import Data
from soc.experiment.testmem import TestMemory # test only for instructions
from soc.regfile.regfiles import StateRegs, FastRegs
from soc.config.ifetch import ConfigFetchUnit
from soc.decoder.power_enums import MicrOp
from soc.debug.dmi import CoreDebug, DMIInterface
+from soc.debug.jtag import JTAG
+from soc.config.pinouts import get_pinspecs
from soc.config.state import CoreState
from soc.interrupts.xics import XICS_ICP, XICS_ICS
from soc.bus.simple_gpio import SimpleGPIO
+from soc.clock.select import ClockSelect
+from soc.clock.dummypll import DummyPLL
+
from nmutil.util import rising_edge
-class TestIssuer(Elaboratable):
+class TestIssuerInternal(Elaboratable):
"""TestIssuer - reads instructions from TestMemory and issues them
efficiency and speed is not the main goal here: functional correctness is.
"""
def __init__(self, pspec):
+ # JTAG interface. add this right at the start because if it's
+ # added it *modifies* the pspec, by adding enable/disable signals
+ # for parts of the rest of the core
+ self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
+ if self.jtag_en:
+ subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
+ 'pwm', 'sd0', 'sdr'}
+ self.jtag = JTAG(get_pinspecs(subset=subset))
+ # add signals to pspec to enable/disable icache and dcache
+ # (or data and intstruction wishbone if icache/dcache not included)
+ # https://bugs.libre-soc.org/show_bug.cgi?id=520
+ # TODO: do we actually care if these are not domain-synchronised?
+ # honestly probably not.
+ pspec.wb_icache_en = self.jtag.wb_icache_en
+ pspec.wb_dcache_en = self.jtag.wb_dcache_en
+
# add interrupt controller?
self.xics = hasattr(pspec, "xics") and pspec.xics == True
if self.xics:
self.simple_gpio = SimpleGPIO()
self.gpio_o = self.simple_gpio.gpio_o
- # main instruction core
+ # main instruction core25
self.core = core = NonProductionCore(pspec)
- # instruction decoder
+ # instruction decoder. goes into Trap Record
pdecode = create_pdecode()
self.cur_state = CoreState("cur") # current state (MSR/PC/EINT)
- self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state)
+ self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
+ opkls=IssuerDecode2ToOperand)
# Test Instruction memory
self.imem = ConfigFetchUnit(pspec).fu
m.submodules.core = core = DomainRenamer("coresync")(self.core)
m.submodules.imem = imem = self.imem
m.submodules.dbg = dbg = self.dbg
+ if self.jtag_en:
+ m.submodules.jtag = jtag = self.jtag
+ # TODO: UART2GDB mux, here, from external pin
+ # see https://bugs.libre-soc.org/show_bug.cgi?id=499
+ sync += dbg.dmi.connect_to(jtag.dmi)
cur_state = self.cur_state
m.submodules.simple_gpio = simple_gpio = self.simple_gpio
# connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
- if self.gpio and self.xics:
- comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
+ # XXX causes litex ECP5 test to get wrong idea about input and output
+ # (but works with verilator sim *sigh*)
+ #if self.gpio and self.xics:
+ # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
# instruction decoder
pdecode = create_pdecode()
core_sync = ClockDomain("coresync")
m.domains += cd_por, cd_sync, core_sync
+ ti_rst = Signal(reset_less=True)
delay = Signal(range(4), reset=3)
with m.If(delay != 0):
m.d.por += delay.eq(delay - 1)
comb += cd_por.clk.eq(ClockSignal())
- comb += core_sync.clk.eq(ClockSignal())
- # power-on reset delay
- comb += core.core_reset_i.eq(delay != 0 | dbg.core_rst_o)
+
+ # power-on reset delay
+ core_rst = ResetSignal("coresync")
+ comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
+ comb += core_rst.eq(ti_rst)
# busy/halted signals from core
comb += self.busy_o.eq(core.busy_o)
sync += core.e.eq(0)
sync += core.raw_insn_i.eq(0)
sync += core.bigendian_i.eq(0)
- with m.If(~dbg.core_stop_o & ~core.core_reset_i):
+ with m.If(~dbg.core_stop_o & ~core_rst):
# instruction allowed to go: start by reading the PC
# capture the PC and also drop it into Insn Memory
# we have joined a pair of combinatorial memory
def external_ports(self):
ports = self.pc_i.ports()
ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
- ClockSignal(), ResetSignal(),
]
- ports += list(self.dbg.dmi.ports())
+
+ if self.jtag_en:
+ ports += list(self.jtag.external_ports())
+ else:
+ # don't add DMI if JTAG is enabled
+ ports += list(self.dbg.dmi.ports())
+
ports += list(self.imem.ibus.fields.values())
ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
return list(self)
+class TestIssuer(Elaboratable):
+ def __init__(self, pspec):
+ self.ti = TestIssuerInternal(pspec)
+
+ self.pll = DummyPLL()
+
+ # PLL direct clock or not
+ self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
+
+ def elaborate(self, platform):
+ m = Module()
+ comb = m.d.comb
+
+ # TestIssuer runs at direct clock
+ m.submodules.ti = ti = self.ti
+ cd_int = ClockDomain("coresync")
+
+ if self.pll_en:
+ # ClockSelect runs at PLL output internal clock rate
+ m.submodules.pll = pll = self.pll
+
+ # add clock domains from PLL
+ cd_pll = ClockDomain("pllclk")
+ m.domains += cd_pll
+
+ # PLL clock established. has the side-effect of running clklsel
+ # at the PLL's speed (see DomainRenamer("pllclk") above)
+ pllclk = ClockSignal("pllclk")
+ comb += pllclk.eq(pll.clk_pll_o)
+
+ # wire up external 24mhz to PLL
+ comb += pll.clk_24_i.eq(ClockSignal())
+
+ # now wire up ResetSignals. don't mind them being in this domain
+ pll_rst = ResetSignal("pllclk")
+ comb += pll_rst.eq(ResetSignal())
+
+ # internal clock is set to selector clock-out. has the side-effect of
+ # running TestIssuer at this speed (see DomainRenamer("intclk") above)
+ intclk = ClockSignal("coresync")
+ if self.pll_en:
+ comb += intclk.eq(pll.clk_pll_o)
+ else:
+ comb += intclk.eq(ClockSignal())
+
+ return m
+
+ def ports(self):
+ return list(self.ti.ports()) + list(self.pll.ports()) + \
+ [ClockSignal(), ResetSignal()]
+
+ def external_ports(self):
+ ports = self.ti.external_ports()
+ ports.append(ClockSignal())
+ ports.append(ResetSignal())
+ if self.pll_en:
+ ports.append(self.pll.clk_sel_i)
+ ports.append(self.pll.pll_18_o)
+ ports.append(self.pll.clk_lck_o)
+ return ports
+
+
if __name__ == '__main__':
units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
'spr': 1,
projects / soc.git / blobdiff