reduce clkcsel ls180 width (2 pins), rename pll_18 signal

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 6243389c76cb932c18d7146900ce5eade4d091f9..d662dff4c20e7904e6ca7cb3ae2ceaa6f03b6e06 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -37,7 +37,8 @@ from soc.config.pinouts import get_pinspecs
 from soc.config.state import CoreState
 from soc.interrupts.xics import XICS_ICP, XICS_ICS
 from soc.bus.simple_gpio import SimpleGPIO
-from soc.clock.select import ClockSelect, DummyPLL
+from soc.clock.select import ClockSelect
+from soc.clock.dummypll import DummyPLL
 
 
 from nmutil.util import rising_edge
@@ -60,6 +61,9 @@ class TestIssuerInternal(Elaboratable):
             self.jtag = JTAG(get_pinspecs(subset=subset))
             # add signals to pspec to enable/disable icache and dcache
             # (or data and intstruction wishbone if icache/dcache not included)
+            # https://bugs.libre-soc.org/show_bug.cgi?id=520
+            # TODO: do we actually care if these are not domain-synchronised?
+            # honestly probably not.
             pspec.wb_icache_en = self.jtag.wb_icache_en
             pspec.wb_dcache_en = self.jtag.wb_dcache_en
 
@@ -171,7 +175,7 @@ class TestIssuerInternal(Elaboratable):
             m.d.por += delay.eq(delay - 1)
         comb += cd_por.clk.eq(ClockSignal())
 
-        # power-on reset delay 
+        # power-on reset delay
         core_rst = ResetSignal("coresync")
         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
         comb += core_rst.eq(ti_rst)
@@ -456,10 +460,11 @@ class TestIssuer(Elaboratable):
         self.ti = TestIssuerInternal(pspec)
 
         self.pll = DummyPLL()
-        self.clksel = ClockSelect()
 
         # PLL direct clock or not
         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
+        if self.pll_en:
+            self.pll_18_o = Signal(reset_less=True)
 
     def elaborate(self, platform):
         m = Module()
@@ -469,50 +474,51 @@ class TestIssuer(Elaboratable):
         m.submodules.ti = ti = self.ti
         cd_int = ClockDomain("coresync")
 
-        # ClockSelect runs at PLL output internal clock rate
-        m.submodules.clksel = clksel = DomainRenamer("pllclk")(self.clksel)
-        m.submodules.pll = pll = self.pll
+        if self.pll_en:
+            # ClockSelect runs at PLL output internal clock rate
+            m.submodules.pll = pll = self.pll
+
+            # add clock domains from PLL
+            cd_pll = ClockDomain("pllclk")
+            m.domains += cd_pll
+
+            # PLL clock established.  has the side-effect of running clklsel
+            # at the PLL's speed (see DomainRenamer("pllclk") above)
+            pllclk = ClockSignal("pllclk")
+            comb += pllclk.eq(pll.clk_pll_o)
+
+            # wire up external 24mhz to PLL
+            comb += pll.clk_24_i.eq(ClockSignal())
 
-        # add 2 clock domains established above...
-        cd_pll = ClockDomain("pllclk")
-        m.domains += cd_pll
+            # output 18 mhz PLL test signal
+            comb += self.pll_18_o.eq(pll.pll_18_o)
+
+            # now wire up ResetSignals.  don't mind them being in this domain
+            pll_rst = ResetSignal("pllclk")
+            comb += pll_rst.eq(ResetSignal())
 
         # internal clock is set to selector clock-out.  has the side-effect of
         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
         intclk = ClockSignal("coresync")
         if self.pll_en:
-            comb += intclk.eq(clksel.core_clk_o)
+            comb += intclk.eq(pll.clk_pll_o)
         else:
             comb += intclk.eq(ClockSignal())
 
-        # PLL clock established.  has the side-effect of running clklsel
-        # at the PLL's speed (see DomainRenamer("pllclk") above)
-        pllclk = ClockSignal("pllclk")
-        comb += pllclk.eq(pll.clk_pll_o)
-
-        # wire up external 24mhz to PLL and clksel
-        comb += clksel.clk_24_i.eq(ClockSignal())
-        comb += pll.clk_24_i.eq(clksel.clk_24_i)
-
-        # now wire up ResetSignals.  don't mind them all being in this domain
-        #int_rst = ResetSignal("coresync")
-        pll_rst = ResetSignal("pllclk")
-        #comb += int_rst.eq(ResetSignal())
-        comb += pll_rst.eq(ResetSignal())
-
         return m
 
     def ports(self):
         return list(self.ti.ports()) + list(self.pll.ports()) + \
-               [ClockSignal(), ResetSignal()] + \
-               list(self.clksel.ports())
+               [ClockSignal(), ResetSignal()]
 
     def external_ports(self):
         ports = self.ti.external_ports()
         ports.append(ClockSignal())
         ports.append(ResetSignal())
-        ports.append(self.clksel.clk_sel_i)
-        ports.append(self.clksel.pll_48_o)
+        if self.pll_en:
+            ports.append(self.pll.clk_sel_i)
+            ports.append(self.pll_18_o)
+            ports.append(self.pll.pll_lck_o)
         return ports