sorting out missing clock somewhere

[soc.git] / src / soc / simple / issuer_verilog.py

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 30ca32b43ce938a356453c615a9938de739fb4bd..92ec2f54a25815ec82e7c7948c6a47a1d785610b 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -13,7 +13,10 @@ if __name__ == '__main__':
                                      "verilog generator")
     parser.add_argument("output_filename")
     parser.add_argument("--enable-xics", action="store_true",
-                        help="Disable interrupts",
+                        help="Enable interrupts",
+                        default=True)
+    parser.add_argument("--enable-core", action="store_true",
+                        help="Enable main core",
                         default=True)
     parser.add_argument("--use-pll", action="store_true", help="Enable pll",
                         default=False)
@@ -46,7 +49,7 @@ if __name__ == '__main__':
                          # set to 32 to make data wishbone bus 32-bit
                          #wb_data_wid=32,
                          xics=args.enable_xics, # XICS interrupt controller
-                         #nocore=True,          # to help test coriolis2 ioring
+                         nocore=not args.enable_core, # test coriolis2 ioring
                          use_pll=args.use_pll,  # bypass PLL
                          gpio=args.enable_testgpio, # for test purposes
                          debug=args.debug,      # set to jtag or dmi