sorting out missing clock somewhere

[soc.git] / src / soc / simple / issuer_verilog.py

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 820e5fd32ddfb3603efcd53b0639d1eb22080ff7..92ec2f54a25815ec82e7c7948c6a47a1d785610b 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -1,7 +1,7 @@
 """simple core issuer verilog generator
 """
 
-import sys
+import argparse
 from nmigen.cli import verilog
 
 from soc.config.test.test_loadstore import TestMemPspec
@@ -9,14 +9,35 @@ from soc.simple.issuer import TestIssuer
 
 
 if __name__ == '__main__':
+    parser = argparse.ArgumentParser(description="Simple core issuer " \
+                                     "verilog generator")
+    parser.add_argument("output_filename")
+    parser.add_argument("--enable-xics", action="store_true",
+                        help="Enable interrupts",
+                        default=True)
+    parser.add_argument("--enable-core", action="store_true",
+                        help="Enable main core",
+                        default=True)
+    parser.add_argument("--use-pll", action="store_true", help="Enable pll",
+                        default=False)
+    parser.add_argument("--enable-testgpio", action="store_true",
+                        help="Disable gpio pins",
+                        default=False)
+    parser.add_argument("--debug", default="jtag", help="Select debug " \
+                        "interface [jtag | dmi] [default jtag]")
+
+    args = parser.parse_args()
+
+    print(args)
+
     units = {'alu': 1,
              'cr': 1, 'branch': 1, 'trap': 1,
-            'logical': 1,
+             'logical': 1,
              'spr': 1,
              'div': 1,
              'mul': 1,
              'shiftrot': 1
-                }
+            }
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
                          imem_ifacetype='bare_wb',
                          addr_wid=48,
@@ -27,13 +48,15 @@ if __name__ == '__main__':
                          imem_reg_wid=64,
                          # set to 32 to make data wishbone bus 32-bit
                          #wb_data_wid=32,
-                         xics=True,
-                         gpio=False, # for test purposes
-                         debug="jtag", # set to jtag or dmi
+                         xics=args.enable_xics, # XICS interrupt controller
+                         nocore=not args.enable_core, # test coriolis2 ioring
+                         use_pll=args.use_pll,  # bypass PLL
+                         gpio=args.enable_testgpio, # for test purposes
+                         debug=args.debug,      # set to jtag or dmi
                          units=units)
 
     dut = TestIssuer(pspec)
 
     vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")
-    with open(sys.argv[1], "w") as f:
+    with open(args.output_filename, "w") as f:
         f.write(vl)