soc.simple.test: Rename setup_test_memory to avoid nosetest calling it

[soc.git] / src / soc / simple / test / test_core.py

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 2f588f2600e71fc23c3f5b39e335cd259390a6fb..194c007594489869a57d0a103c810f13b15583e2 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -25,7 +25,7 @@ from openpower.endian import bigendian
 from soc.simple.core import NonProductionCore
 from soc.experiment.compalu_multi import find_ok  # hack
 
-from soc.fu.compunits.test.test_compunit import (setup_test_memory,
+from soc.fu.compunits.test.test_compunit import (setup_tst_memory,
                                                  check_sim_memory)
 
 # test with ALU data and Logical data
@@ -278,7 +278,7 @@ class TestRunner(FHDLTestCase):
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
 
-                yield from setup_test_memory(l0, sim)
+                yield from setup_tst_memory(l0, sim)
                 yield from setup_regs(core, test)
 
                 index = sim.pc.CIA.value//4