dut.assertEqual(e_ov, ov, "ov mismatch %s" % (repr(code)))
dut.assertEqual(e_ca, ca, "ca mismatch %s" % (repr(code)))
+ # Check the PC as well
+ state = core.regs.rf['state']
+ pc = yield state.r_ports['cia'].data_o
+ e_pc = sim.pc.CIA.value
+ dut.assertEqual(e_pc, pc)
+
def wait_for_busy_hi(cu):
while True: