from soc.fu.cr.test.test_pipe_caller import CRTestCase
from soc.fu.branch.test.test_pipe_caller import BranchTestCase
from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
-from openpower.test.general.overlap_hazards import HazardTestCase
-from openpower.util import spr_to_fast_reg
+from openpower.test.general.overlap_hazards import (HazardTestCase,
+ RandomHazardTestCase)
+from openpower.util import spr_to_fast_reg, spr_to_state_reg
from openpower.consts import StateRegsEnum
# list of SPRs that are controlled and managed by the MMU
-mmu_sprs = ["PRTBL", "DSISR", "DAR", "PIDR"]
+mmu_sprs = ["PRTBL", "PIDR"]
+ldst_sprs = ["DAR", "DSISR"]
def set_mmu_spr(name, i, val, core): # important keep pep8 formatting
yield fsm.mmu.l_in.rs.eq(val)
yield
yield fsm.mmu.l_in.mtspr.eq(0)
- print("mmu_spr was updated")
+ while True:
+ done = yield fsm.mmu.l_out.done
+ if done:
+ break
+ yield
+ yield
+ print("mmu_spr %s %d was updated %x" % (name, i, val))
+
+
+def set_ldst_spr(name, i, val, core): # important keep pep8 formatting
+ ldst = core.fus.get_fu("mmu0").alu.ldst # awkward to get at but it works
+ yield ldst.sprval_in.eq(val)
+ yield ldst.mmu_set_spr.eq(1)
+ if name == 'DAR':
+ yield ldst.mmu_set_dar.eq(1)
+ yield
+ yield ldst.mmu_set_dar.eq(0)
+ else:
+ yield ldst.mmu_set_dsisr.eq(1)
+ yield
+ yield ldst.mmu_set_dsisr.eq(0)
+ yield ldst.mmu_set_spr.eq(0)
+ print("ldst_spr %s %d was updated %x" % (name, i, val))
def setup_regs(pdecode2, core, test):
# setting both fast and slow SPRs from test data
fregs = core.regs.fast
+ stateregs = core.regs.state
sregs = core.regs.spr
for sprname, val in test.sprs.items():
if isinstance(val, SelectableInt):
sprname = spr_dict[sprname].SPR
if sprname == 'XER':
continue
+ print ('set spr %s val %x' % (sprname, val))
+
fast = spr_to_fast_reg(sprname)
- if fast is None:
+ state = spr_to_state_reg(sprname)
+
+ if fast is None and state is None:
# match behaviour of SPRMap in power_decoder2.py
for i, x in enumerate(SPR):
if sprname == x.name:
- print("setting slow SPR %d (%s) to %x" %
- (i, sprname, val))
- if sprname not in mmu_sprs:
- yield sregs.memory._array[i].eq(val)
+ print("setting slow SPR %d (%s/%d) to %x" %
+ (i, sprname, x.value, val))
+ if sprname in mmu_sprs:
+ yield from set_mmu_spr(sprname, x.value, val, core)
+ elif sprname in ldst_sprs:
+ yield from set_ldst_spr(sprname, x.value, val, core)
else:
- yield from set_mmu_spr(sprname, i, val, core)
+ yield sregs.memory._array[i].eq(val)
+ elif state is not None:
+ print("setting state reg %d (%s) to %x" %
+ (state, sprname, val))
+ if stateregs.unary:
+ rval = stateregs.regs[state].reg
+ else:
+ rval = stateregs.memory._array[state]
+ yield rval.eq(val)
else:
print("setting fast reg %d (%s) to %x" %
(fast, sprname, val))
comb = m.d.comb
instruction = Signal(32)
+ units = {'alu': 3, 'cr': 1, 'branch': 1, 'trap': 1,
+ 'spr': 1,
+ 'logical': 1,
+ 'mul': 3,
+ 'div': 1, 'shiftrot': 1}
+
pspec = TestMemPspec(ldst_ifacetype='testpi',
imem_ifacetype='',
addr_wid=48,
mask_wid=8,
+ units=units,
+ allow_overlap=True,
reg_wid=64)
cur_state = CoreState("cur") # current state (MSR/PC/SVSTATE)
pdecode2 = PowerDecode2(None, state=cur_state,
- opkls=IssuerDecode2ToOperand,
+ #opkls=IssuerDecode2ToOperand,
svp64_en=True, # self.svp64_en,
regreduce_en=False, #self.regreduce_en
)
# ask the decoder to decode this binary data (endian'd)
yield instruction.eq(ins) # raw binary instr.
yield Settle()
- yield core.p.i_valid.eq(1)
- yield
- o_ready = yield core.p.o_ready
- while True:
- if o_ready:
- break
- yield
- o_ready = yield core.p.o_ready
- yield core.p.i_valid.eq(0)
-
- # set operand and get inputs
- yield from wait_for_busy_clear(core)
print("sim", code)
# call simulated operation
yield stateregs.regs[pc_regnum].reg.eq(pc)
yield Settle()
+ yield core.p.i_valid.eq(1)
+ yield
+ o_ready = yield core.p.o_ready
+ while True:
+ if o_ready:
+ break
+ yield
+ o_ready = yield core.p.o_ready
+ yield core.p.i_valid.eq(0)
+
+ # set operand and get inputs
+ yield from wait_for_busy_clear(core)
+
+ # synchronised (non-overlap) is fine to check
+ if not core.allow_overlap:
+ # register check
+ yield from check_regs(self, sim, core, test, code)
+
+ # Memory check
+ yield from check_mem(self, sim, core, test, code)
+
+ # non-overlap mode is only fine to check right at the end
+ if core.allow_overlap:
+ # wait until all settled
+ # XXX really this should be in DMI, which should in turn
+ # use issuer.any_busy to not send back "stopped" signal
+ while (yield core.o.any_busy_o):
+ yield
+ yield Settle()
+
# register check
yield from check_regs(self, sim, core, test, code)
# Memory check
yield from check_mem(self, sim, core, test, code)
+ # give a couple extra clock cycles for gtkwave display to be happy
+ yield
+ yield
+
sim.add_sync_process(process)
with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
traces=[]):
unittest.main(exit=False)
suite = unittest.TestSuite()
suite.addTest(TestRunner(HazardTestCase().test_data))
+ suite.addTest(TestRunner(RandomHazardTestCase().test_data))
#suite.addTest(TestRunner(LDSTTestCase().test_data))
#suite.addTest(TestRunner(CRTestCase().test_data))
#suite.addTest(TestRunner(ShiftRotTestCase().test_data))