* https://bugs.libre-soc.org/show_bug.cgi?id=363
"""
from nmigen import Module, Signal, Cat
-from nmigen.back.pysim import Simulator, Delay, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
+
from nmutil.formaltest import FHDLTestCase
from nmigen.cli import rtlil
import unittest
from soc.decoder.power_decoder import create_pdecode
from soc.decoder.power_decoder2 import PowerDecode2
-from soc.simple.issuer import TestIssuer
+from soc.simple.issuer import TestIssuerInternal
from soc.experiment.compalu_multi import find_ok # hack
from soc.config.test.test_loadstore import TestMemPspec
from soc.fu.alu.test.test_pipe_caller import ALUTestCase
from soc.fu.div.test.test_pipe_caller import DivTestCases
from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
-#from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
+from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
from soc.fu.cr.test.test_pipe_caller import CRTestCase
#from soc.fu.branch.test.test_pipe_caller import BranchTestCase
#from soc.fu.spr.test.test_pipe_caller import SPRTestCase
mask_wid=8,
imem_reg_wid=64,
#wb_data_width=32,
+ use_pll=False,
+ nocore=False,
+ xics=False,
+ gpio=False,
reg_wid=64)
- m.submodules.issuer = issuer = TestIssuer(pspec)
+ m.submodules.issuer = issuer = TestIssuerInternal(pspec)
imem = issuer.imem._get_memory()
core = issuer.core
dmi = issuer.dbg.dmi
yield
yield
+ # get CR
+ cr = yield from get_dmi(dmi, DBGCore.CR)
+ print ("after test %s cr value %x" % (test.name, cr))
+
+ # get XER
+ xer = yield from get_dmi(dmi, DBGCore.XER)
+ print ("after test %s XER value %x" % (test.name, xer))
+
# test of dmi reg get
for int_reg in range(32):
yield from set_dmi(dmi, DBGCore.GSPR_IDX, int_reg)
unittest.main(exit=False)
suite = unittest.TestSuite()
# suite.addTest(TestRunner(HelloTestCases.test_data))
- suite.addTest(TestRunner(DivTestCases().test_data))
+ #suite.addTest(TestRunner(DivTestCases().test_data))
# suite.addTest(TestRunner(AttnTestCase.test_data))
- suite.addTest(TestRunner(GeneralTestCases.test_data))
- suite.addTest(TestRunner(LDSTTestCase().test_data))
- # suite.addTest(TestRunner(CRTestCase().test_data))
- # suite.addTest(TestRunner(ShiftRotTestCase.test_data))
- suite.addTest(TestRunner(LogicalTestCase().test_data))
+ #suite.addTest(TestRunner(GeneralTestCases.test_data))
+ #suite.addTest(TestRunner(LDSTTestCase().test_data))
+ #suite.addTest(TestRunner(CRTestCase().test_data))
+ #suite.addTest(TestRunner(ShiftRotTestCase().test_data))
+ #suite.addTest(TestRunner(LogicalTestCase().test_data))
suite.addTest(TestRunner(ALUTestCase().test_data))
# suite.addTest(TestRunner(BranchTestCase.test_data))
# suite.addTest(TestRunner(SPRTestCase.test_data))