set defaults in pspec

[soc.git] / src / soc / simple / test / test_issuer.py

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index f83c17b58db73c971acab9357c68933bb07dadbc..012e5b198a4c5826df5d9d0a00de9776e0f64b8a 100644 (file)
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -5,7 +5,11 @@ related bugs:
  * https://bugs.libre-soc.org/show_bug.cgi?id=363
 """
 from nmigen import Module, Signal, Cat
-from nmigen.back.pysim import Simulator, Delay, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
+
 from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 import unittest
@@ -17,7 +21,7 @@ from soc.config.endian import bigendian
 from soc.decoder.power_decoder import create_pdecode
 from soc.decoder.power_decoder2 import PowerDecode2
 
-from soc.simple.issuer import TestIssuer
+from soc.simple.issuer import TestIssuerInternal
 from soc.experiment.compalu_multi import find_ok  # hack
 
 from soc.config.test.test_loadstore import TestMemPspec
@@ -32,7 +36,7 @@ from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
 from soc.fu.alu.test.test_pipe_caller import ALUTestCase
 from soc.fu.div.test.test_pipe_caller import DivTestCases
 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
-#from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
+from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
 from soc.fu.cr.test.test_pipe_caller import CRTestCase
 #from soc.fu.branch.test.test_pipe_caller import BranchTestCase
 #from soc.fu.spr.test.test_pipe_caller import SPRTestCase
@@ -143,8 +147,12 @@ class TestRunner(FHDLTestCase):
                              mask_wid=8,
                              imem_reg_wid=64,
                              #wb_data_width=32,
+                             use_pll=False,
+                             nocore=False,
+                             xics=False,
+                             gpio=False,
                              reg_wid=64)
-        m.submodules.issuer = issuer = TestIssuer(pspec)
+        m.submodules.issuer = issuer = TestIssuerInternal(pspec)
         imem = issuer.imem._get_memory()
         core = issuer.core
         dmi = issuer.dbg.dmi
@@ -281,6 +289,10 @@ class TestRunner(FHDLTestCase):
                 cr = yield from get_dmi(dmi, DBGCore.CR)
                 print ("after test %s cr value %x" % (test.name, cr))
 
+                # get XER
+                xer = yield from get_dmi(dmi, DBGCore.XER)
+                print ("after test %s XER value %x" % (test.name, xer))
+
                 # test of dmi reg get
                 for int_reg in range(32):
                     yield from set_dmi(dmi, DBGCore.GSPR_IDX, int_reg) 
@@ -299,13 +311,13 @@ if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
     # suite.addTest(TestRunner(HelloTestCases.test_data))
-    suite.addTest(TestRunner(DivTestCases().test_data))
+    #suite.addTest(TestRunner(DivTestCases().test_data))
     # suite.addTest(TestRunner(AttnTestCase.test_data))
-    suite.addTest(TestRunner(GeneralTestCases.test_data))
-    suite.addTest(TestRunner(LDSTTestCase().test_data))
-    suite.addTest(TestRunner(CRTestCase().test_data))
-    # suite.addTest(TestRunner(ShiftRotTestCase.test_data))
-    suite.addTest(TestRunner(LogicalTestCase().test_data))
+    #suite.addTest(TestRunner(GeneralTestCases.test_data))
+    #suite.addTest(TestRunner(LDSTTestCase().test_data))
+    #suite.addTest(TestRunner(CRTestCase().test_data))
+    #suite.addTest(TestRunner(ShiftRotTestCase().test_data))
+    #suite.addTest(TestRunner(LogicalTestCase().test_data))
     suite.addTest(TestRunner(ALUTestCase().test_data))
     # suite.addTest(TestRunner(BranchTestCase.test_data))
     # suite.addTest(TestRunner(SPRTestCase.test_data))