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[soc.git]
/
src
/
soc
/
simple
/
test
/
test_runner.py
diff --git
a/src/soc/simple/test/test_runner.py
b/src/soc/simple/test/test_runner.py
index e4e109ec3cdea9e1bc1c56a5facb0bd673c7ccda..32c19db5d119a93cf4a463be60c4dd0e1190e9b7 100644
(file)
--- a/
src/soc/simple/test/test_runner.py
+++ b/
src/soc/simple/test/test_runner.py
@@
-381,6
+381,8
@@
class TestRunner(FHDLTestCase):
simrun = SimRunner(self, m, pspec)
# run core clock at same rate as test clock
+ # XXX this has to stay here! TODO, work out why,
+ # but Simulation-only fails without it
intclk = ClockSignal("coresync")
comb += intclk.eq(ClockSignal())