move pc_i and svstate_i to HDLRunner

[soc.git] / src / soc / simple / test / test_runner.py

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index ca2b93414497bfa262733833f1c27e6665f0c3b0..af42368af3106c9bd2c911a21b0f1d0b27c967f0 100644 (file)
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -179,10 +179,10 @@ class SimRunner(StateRunner):
 
 
 class HDLRunner(StateRunner):
-    def __init__(self, dut, m, pspec, pc_i, svstate_i):
+    def __init__(self, dut, m, pspec):
         self.dut = dut
-        self.pc_i = pc_i
-        self.svstate_i = svstate_i
+        self.pc_i = Signal(32)
+        self.svstate_i = Signal(64)
 
         #hard_reset = Signal(reset_less=True)
         self.issuer = TestIssuerInternal(pspec)
@@ -192,6 +192,10 @@ class HDLRunner(StateRunner):
         m.submodules.issuer = self.issuer
         self.dmi = self.issuer.dbg.dmi
 
+        comb = m.d.comb
+        comb += self.issuer.pc_i.data.eq(self.pc_i)
+        comb += self.issuer.svstate_i.data.eq(self.svstate_i)
+
     def prepare_for_test(self, test):
         self.test = test
 
@@ -365,9 +369,7 @@ class TestRunner(FHDLTestCase):
         # StateRunner.setup_for_test()
 
         if self.run_hdl:
-            pc_i = Signal(32)
-            svstate_i = Signal(64)
-            hdlrun = HDLRunner(self, m, pspec, pc_i, svstate_i)
+            hdlrun = HDLRunner(self, m, pspec)
 
         if self.run_sim:
             simrun = SimRunner(self, m, pspec)
@@ -376,10 +378,6 @@ class TestRunner(FHDLTestCase):
         intclk = ClockSignal("coresync")
         comb += intclk.eq(ClockSignal())
 
-        if self.run_hdl:
-            comb += hdlrun.issuer.pc_i.data.eq(pc_i)
-            comb += hdlrun.issuer.svstate_i.data.eq(svstate_i)
-
         # nmigen Simulation - everything runs around this, so it
         # still has to be created.
         sim = Simulator(m)