Revert "move coresync clock synchronisation into HDLRunner"

[soc.git] / src / soc / simple / test / test_runner.py

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 09481697759c1d2ad8892d542f5bef1454085fae..e4e109ec3cdea9e1bc1c56a5facb0bd673c7ccda 100644 (file)
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -201,10 +201,6 @@ class HDLRunner(StateRunner):
         comb += self.issuer.pc_i.data.eq(self.pc_i)
         comb += self.issuer.svstate_i.data.eq(self.svstate_i)
 
-        # run core clock at same rate as test clock
-        intclk = ClockSignal("coresync")
-        comb += intclk.eq(ClockSignal())
-
     def prepare_for_test(self, test):
         self.test = test
 
@@ -384,6 +380,10 @@ class TestRunner(FHDLTestCase):
         if self.run_sim:
             simrun = SimRunner(self, m, pspec)
 
+        # run core clock at same rate as test clock
+        intclk = ClockSignal("coresync")
+        comb += intclk.eq(ClockSignal())
+
         # nmigen Simulation - everything runs around this, so it
         # still has to be created.
         sim = Simulator(m)