Allow the formal engine to perform a same-cycle result in the ALU

[soc.git] / src / soc / simple / test / teststate.py

diff --git a/src/soc/simple/test/teststate.py b/src/soc/simple/test/teststate.py
index 3a65c9dc7628f27c72963392c72470e003411777..cc62c5da4b4cceb3990c13e1476da72f1f96a8bf 100644 (file)
--- a/src/soc/simple/test/teststate.py
+++ b/src/soc/simple/test/teststate.py
@@ -12,10 +12,20 @@ from openpower.test.state import (State, state_add, state_factory,
 from soc.fu.compunits.test.test_compunit import get_l0_mem
 
 class HDLState(State):
+    """HDLState: Obtains registers and memory from an nmigen simulator
+    object by implementing State class methods.
+    """
     def __init__(self, core):
         super().__init__()
         self.core = core
 
+    def get_fpregs(self):
+        if False:
+            yield
+        self.fpregs = []
+        for i in range(32):
+            self.fpregs.append(0)
+
     def get_intregs(self):
         self.intregs = []
         for i in range(32):
@@ -29,7 +39,7 @@ class HDLState(State):
     def get_crregs(self):
         self.crregs = []
         for i in range(8):
-            rval = yield self.core.regs.cr.regs[i].reg
+            rval = yield self.core.regs.cr.regs[7-i].reg
             self.crregs.append(rval)
         log("class hdl cr regs", list(map(hex, self.crregs)))
 
@@ -45,14 +55,18 @@ class HDLState(State):
     def get_pc(self):
         self.pcl = []
         self.state = self.core.regs.state
+        # relies on the state.r_port being permanently held as PC
         self.pc = yield self.state.r_ports['cia'].o_data
         self.pcl.append(self.pc)
         log("class hdl pc", hex(self.pc))
 
     def get_mem(self):
+        self.mem = {}
         # get the underlying HDL-simulated memory from the L0CacheBuffer
+        if hasattr(self.core, "icache"):
+            # err temporarily ignore memory
+            return # XXX have to work out how to deal with wb_get
         hdlmem = get_l0_mem(self.core.l0)
-        self.mem = {}
         for i in range(hdlmem.depth):
             value = yield hdlmem._array[i] # should not really do this
             self.mem[i*8] = value