super().__init__()
self.core = core
+ def get_fpregs(self):
+ if False:
+ yield
+ self.fpregs = []
+ for i in range(32):
+ self.fpregs.append(0)
+
def get_intregs(self):
self.intregs = []
for i in range(32):
log("class hdl pc", hex(self.pc))
def get_mem(self):
+ self.mem = {}
# get the underlying HDL-simulated memory from the L0CacheBuffer
+ if hasattr(self.core, "icache"):
+ # err temporarily ignore memory
+ return # XXX have to work out how to deal with wb_get
hdlmem = get_l0_mem(self.core.l0)
- self.mem = {}
for i in range(hdlmem.depth):
value = yield hdlmem._array[i] # should not really do this
self.mem[i*8] = value