Allow the formal engine to perform a same-cycle result in the ALU

[soc.git] / src / soc / simple / test / teststate.py

diff --git a/src/soc/simple/test/teststate.py b/src/soc/simple/test/teststate.py
index 8d6c32bd8ec2ce1f9e9170a685947a05eef85004..cc62c5da4b4cceb3990c13e1476da72f1f96a8bf 100644 (file)
--- a/src/soc/simple/test/teststate.py
+++ b/src/soc/simple/test/teststate.py
@@ -1,75 +1,30 @@
-from openpower.decoder.power_enums import XER_bits
-
-class State:
-    def __init__(self):
-        pass
-
-    def get_intregs(self):
-        pass
-
-    def get_crregs(self):
-        pass
+""" Power ISA test API
 
-    def get_xregs(self):
-        pass
+This module implements the creation, inspection and comparison
+of test states for TestIssuer HDL
 
-    def get_pc(self):
-        pass
+"""
 
-    def get_state(self):
-        yield from self.get_intregs()
-        yield from self.get_crregs()
-        yield from self.get_xregs()
-        yield from self.get_pc()
+from openpower.decoder.power_enums import XER_bits
+from openpower.util import log
+from openpower.test.state import (State, state_add, state_factory,
+                                  TestState,)
+from soc.fu.compunits.test.test_compunit import get_l0_mem
 
-class SimState(State):
-    def __init__(self, sim):
-        self.sim = sim
+class HDLState(State):
+    """HDLState: Obtains registers and memory from an nmigen simulator
+    object by implementing State class methods.
+    """
+    def __init__(self, core):
+        super().__init__()
+        self.core = core
 
-    def get_intregs(self):
+    def get_fpregs(self):
         if False:
             yield
-        self.intregs = []
+        self.fpregs = []
         for i in range(32):
-            simregval = self.sim.gpr[i].asint()
-            self.intregs.append(simregval)
-        print("class sim int regs", list(map(hex, self.intregs)))
-
-    def get_crregs(self):
-        if False:
-            yield
-        self.crregs = []
-        for i in range(8):
-            cri = self.sim.crl[7 - i].get_range().value
-            self.crregs.append(cri)
-        print("class sim cr regs", list(map(hex, self.crregs)))
-
-    def get_xregs(self):
-        if False:
-            yield
-        self.xregs = []
-        self.so = self.sim.spr['XER'][XER_bits['SO']].value
-        self.ov = self.sim.spr['XER'][XER_bits['OV']].value
-        self.ov32 = self.sim.spr['XER'][XER_bits['OV32']].value
-        self.ca = self.sim.spr['XER'][XER_bits['CA']].value
-        self.ca32 = self.sim.spr['XER'][XER_bits['CA32']].value
-        self.ov = self.ov | (self.ov32 << 1)
-        self.ca = self.ca | (self.ca32 << 1)
-        self.xregs.extend((self.so, self.ov, self.ca))
-        print("class sim xregs", list(map(hex, self.xregs)))
-
-    def get_pc(self):
-        if False:
-            yield
-        self.pcl = []
-        self.pc = self.sim.pc.CIA.value
-        self.pcl.append(self.pc)
-        print("class sim pc", hex(self.pc))
-
-
-class HDLState(State):
-    def __init__(self, core):
-        self.core = core
+            self.fpregs.append(0)
 
     def get_intregs(self):
         self.intregs = []
@@ -79,14 +34,14 @@ class HDLState(State):
             else:
                 rval = yield self.core.regs.int.memory._array[i]
             self.intregs.append(rval)
-        print("class hdl int regs", list(map(hex, self.intregs)))
+        log("class hdl int regs", list(map(hex, self.intregs)))
 
     def get_crregs(self):
         self.crregs = []
         for i in range(8):
-            rval = yield self.core.regs.cr.regs[i].reg
+            rval = yield self.core.regs.cr.regs[7-i].reg
             self.crregs.append(rval)
-        print("class hdl cr regs", list(map(hex, self.crregs)))
+        log("class hdl cr regs", list(map(hex, self.crregs)))
 
     def get_xregs(self):
         self.xregs = []
@@ -95,11 +50,27 @@ class HDLState(State):
         self.ov = yield self.xr.regs[self.xr.OV].reg
         self.ca = yield self.xr.regs[self.xr.CA].reg
         self.xregs.extend((self.so, self.ov, self.ca))
-        print("class hdl xregs", list(map(hex, self.xregs)))
+        log("class hdl xregs", list(map(hex, self.xregs)))
 
     def get_pc(self):
         self.pcl = []
         self.state = self.core.regs.state
+        # relies on the state.r_port being permanently held as PC
         self.pc = yield self.state.r_ports['cia'].o_data
         self.pcl.append(self.pc)
-        print("class hdl pc", hex(self.pc))
+        log("class hdl pc", hex(self.pc))
+
+    def get_mem(self):
+        self.mem = {}
+        # get the underlying HDL-simulated memory from the L0CacheBuffer
+        if hasattr(self.core, "icache"):
+            # err temporarily ignore memory
+            return # XXX have to work out how to deal with wb_get
+        hdlmem = get_l0_mem(self.core.l0)
+        for i in range(hdlmem.depth):
+            value = yield hdlmem._array[i] # should not really do this
+            self.mem[i*8] = value
+
+
+# add to State Factory
+state_add('hdl', HDLState)